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301 lines
11 KiB
Python
301 lines
11 KiB
Python
"""RTIO driver for the Fastino 32channel, 16 bit, 2.5 MS/s per channel,
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streaming DAC.
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"""
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from numpy import int32, int64
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from artiq.language.core import kernel, portable, delay, delay_mu
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from artiq.coredevice.rtio import (rtio_output, rtio_output_wide,
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rtio_input_data)
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from artiq.language.units import ns
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from artiq.language.types import TInt32, TList
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class Fastino:
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"""Fastino 32-channel, 16-bit, 2.5 MS/s per channel streaming DAC
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The RTIO PHY supports staging DAC data before transmitting them by writing
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to the DAC RTIO addresses, if a channel is not "held" by setting its bit
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using :meth:`set_hold`, the next frame will contain the update. For the
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DACs held, the update is triggered explicitly by setting the corresponding
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bit using :meth:`set_update`. Update is self-clearing. This enables atomic
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DAC updates synchronized to a frame edge.
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The `log2_width=0` RTIO layout uses one DAC channel per RTIO address and a
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dense RTIO address space. The RTIO words are narrow. (32 bit) and
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few-channel updates are efficient. There is the least amount of DAC state
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tracking in kernels, at the cost of more DMA and RTIO data.
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The setting here and in the RTIO PHY (gateware) must match.
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Other `log2_width` (up to `log2_width=5`) settings pack multiple
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(in powers of two) DAC channels into one group and into one RTIO write.
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The RTIO data width increases accordingly. The `log2_width`
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LSBs of the RTIO address for a DAC channel write must be zero and the
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address space is sparse. For `log2_width=5` the RTIO data is 512 bit wide.
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If `log2_width` is zero, the :meth:`set_dac`/:meth:`set_dac_mu` interface
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must be used. If non-zero, the :meth:`set_group`/:meth:`set_group_mu`
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interface must be used.
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:param channel: RTIO channel number
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:param core_device: Core device name (default: "core")
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:param log2_width: Width of DAC channel group (logarithm base 2).
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Value must match the corresponding value in the RTIO PHY (gateware).
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"""
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kernel_invariants = {"core", "channel", "width", "t_frame"}
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def __init__(self, dmgr, channel, core_device="core", log2_width=0):
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self.channel = channel << 8
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self.core = dmgr.get(core_device)
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self.width = 1 << log2_width
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# frame duration in mu (14 words each 7 clock cycles each 4 ns)
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# self.core.seconds_to_mu(14*7*4*ns) # unfortunately this may round wrong
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assert self.core.ref_period == 1*ns
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self.t_frame = int64(14*7*4)
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@kernel
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def init(self):
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"""Initialize the device.
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* disables RESET, DAC_CLR, enables AFE_PWR
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* clears error counters, enables error counting
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* turns LEDs off
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* clears `hold` and `continuous` on all channels
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* clear and resets interpolators to unit rate change on all
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channels
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It does not change set channel voltages and does not reset the PLLs or clock
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domains.
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Note: On Fastino gateware before v0.2 this may lead to 0 voltage being emitted
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transiently.
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"""
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self.set_cfg(reset=0, afe_power_down=0, dac_clr=0, clr_err=1)
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delay_mu(self.t_frame)
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self.set_cfg(reset=0, afe_power_down=0, dac_clr=0, clr_err=0)
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delay_mu(self.t_frame)
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self.set_continuous(0)
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delay_mu(self.t_frame)
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self.stage_cic(1)
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delay_mu(self.t_frame)
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self.apply_cic(0xffffffff)
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delay_mu(self.t_frame)
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self.set_leds(0)
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delay_mu(self.t_frame)
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self.set_hold(0)
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delay_mu(self.t_frame)
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@kernel
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def write(self, addr, data):
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"""Write data to a Fastino register.
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:param addr: Address to write to.
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:param data: Data to write.
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"""
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rtio_output(self.channel | addr, data)
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@kernel
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def read(self, addr):
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"""Read from Fastino register.
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TODO: untested
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:param addr: Address to read from.
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:return: The data read.
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"""
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raise NotImplementedError
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# rtio_output(self.channel | addr | 0x80)
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# return rtio_input_data(self.channel >> 8)
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@kernel
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def set_dac_mu(self, dac, data):
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"""Write DAC data in machine units.
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:param dac: DAC channel to write to (0-31).
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:param data: DAC word to write, 16 bit unsigned integer, in machine
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units.
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"""
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self.write(dac, data)
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@kernel
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def set_group_mu(self, dac: TInt32, data: TList(TInt32)):
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"""Write a group of DAC channels in machine units.
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:param dac: First channel in DAC channel group (0-31). The `log2_width`
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LSBs must be zero.
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:param data: List of DAC data pairs (2x16 bit unsigned) to write,
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in machine units. Data exceeding group size is ignored.
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If the list length is less than group size, the remaining
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DAC channels within the group are cleared to 0 (machine units).
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"""
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if dac & (self.width - 1):
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raise ValueError("Group index LSBs must be zero")
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rtio_output_wide(self.channel | dac, data)
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@portable
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def voltage_to_mu(self, voltage):
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"""Convert SI Volts to DAC machine units.
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:param voltage: Voltage in SI Volts.
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:return: DAC data word in machine units, 16 bit integer.
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"""
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data = int32(round((0x8000/10.)*voltage)) + int32(0x8000)
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if data < 0 or data > 0xffff:
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raise ValueError("DAC voltage out of bounds")
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return data
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@portable
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def voltage_group_to_mu(self, voltage, data):
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"""Convert SI Volts to packed DAC channel group machine units.
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:param voltage: List of SI Volt voltages.
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:param data: List of DAC channel data pairs to write to.
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Half the length of `voltage`.
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"""
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for i in range(len(voltage)):
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v = self.voltage_to_mu(voltage[i])
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if i & 1:
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v = data[i // 2] | (v << 16)
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data[i // 2] = int32(v)
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@kernel
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def set_dac(self, dac, voltage):
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"""Set DAC data to given voltage.
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:param dac: DAC channel (0-31).
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:param voltage: Desired output voltage.
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"""
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self.write(dac, self.voltage_to_mu(voltage))
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@kernel
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def set_group(self, dac, voltage):
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"""Set DAC group data to given voltage.
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:param dac: DAC channel (0-31).
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:param voltage: Desired output voltage.
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"""
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data = [int32(0)] * (len(voltage) // 2)
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self.voltage_group_to_mu(voltage, data)
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self.set_group_mu(dac, data)
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@kernel
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def update(self, update):
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"""Schedule channels for update.
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:param update: Bit mask of channels to update (32 bit).
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"""
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self.write(0x20, update)
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@kernel
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def set_hold(self, hold):
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"""Set channels to manual update.
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:param hold: Bit mask of channels to hold (32 bit).
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"""
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self.write(0x21, hold)
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@kernel
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def set_cfg(self, reset=0, afe_power_down=0, dac_clr=0, clr_err=0):
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"""Set configuration bits.
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:param reset: Reset SPI PLL and SPI clock domain.
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:param afe_power_down: Disable AFE power.
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:param dac_clr: Assert all 32 DAC_CLR signals setting all DACs to
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mid-scale (0 V).
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:param clr_err: Clear error counters and PLL reset indicator.
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This clears the sticky red error LED. Must be cleared to enable
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error counting.
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"""
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self.write(0x22, (reset << 0) | (afe_power_down << 1) |
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(dac_clr << 2) | (clr_err << 3))
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@kernel
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def set_leds(self, leds):
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"""Set the green user-defined LEDs
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:param leds: LED status, 8 bit integer each bit corresponding to one
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green LED.
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"""
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self.write(0x23, leds)
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@kernel
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def set_continuous(self, channel_mask):
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"""Enable continuous DAC updates on channels regardless of new data
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being submitted.
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"""
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self.write(0x25, channel_mask)
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@kernel
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def stage_cic_mu(self, rate_mantissa, rate_exponent, gain_exponent):
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"""Stage machine unit CIC interpolator configuration.
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"""
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if rate_mantissa < 0 or rate_mantissa >= 1 << 6:
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raise ValueError("rate_mantissa out of bounds")
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if rate_exponent < 0 or rate_exponent >= 1 << 4:
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raise ValueError("rate_exponent out of bounds")
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if gain_exponent < 0 or gain_exponent >= 1 << 6:
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raise ValueError("gain_exponent out of bounds")
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config = rate_mantissa | (rate_exponent << 6) | (gain_exponent << 10)
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self.write(0x26, config)
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@kernel
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def stage_cic(self, rate) -> TInt32:
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"""Compute and stage interpolator configuration.
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This method approximates the desired interpolation rate using a 10 bit
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floating point representation (6 bit mantissa, 4 bit exponent) and
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then determines an optimal interpolation gain compensation exponent
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to avoid clipping. Gains for rates that are powers of two are accurately
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compensated. Other rates lead to overall less than unity gain (but more
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than 0.5 gain).
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The overall gain including gain compensation is
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`actual_rate**order/2**ceil(log2(actual_rate**order))`
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where `order = 3`.
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Returns the actual interpolation rate.
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"""
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if rate <= 0 or rate > 1 << 16:
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raise ValueError("rate out of bounds")
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rate_mantissa = rate
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rate_exponent = 0
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while rate_mantissa > 1 << 6:
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rate_exponent += 1
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rate_mantissa >>= 1
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order = 3
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gain = 1
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for i in range(order):
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gain *= rate_mantissa
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gain_exponent = 0
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while gain > 1 << gain_exponent:
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gain_exponent += 1
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gain_exponent += order*rate_exponent
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assert gain_exponent <= order*16
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self.stage_cic_mu(rate_mantissa - 1, rate_exponent, gain_exponent)
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return rate_mantissa << rate_exponent
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@kernel
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def apply_cic(self, channel_mask):
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"""Apply the staged interpolator configuration on the specified channels.
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Each Fastino channel starting with gateware v0.2 includes a fourth order
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(cubic) CIC interpolator with variable rate change and variable output
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gain compensation (see :meth:`stage_cic`).
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Fastino gateware before v0.2 does not include the interpolators and the
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methods affecting the CICs should not be used.
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Channels using non-unity interpolation rate should have
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continous DAC updates enabled (see :meth:`set_continuous`) unless
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their output is supposed to be constant.
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This method resets and settles the affected interpolators. There will be
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no output updates for the next `order = 3` input samples.
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Affected channels will only accept one input sample per input sample
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period. This method synchronizes the input sample period to the current
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frame on the affected channels.
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If application of new interpolator settings results in a change of the
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overall gain, there will be a corresponding output step.
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"""
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self.write(0x27, channel_mask)
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