mirror of https://github.com/m-labs/artiq.git
fastino: add comments about sideeffects on v0.1
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@ -65,6 +65,9 @@ class Fastino:
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It does not change set channel voltages and does not reset the PLLs or clock
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domains.
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Note: On Fastino gateware before v0.2 this may lead to 0 voltage being emitted
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transiently.
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"""
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self.set_cfg(reset=0, afe_power_down=0, dac_clr=0, clr_err=1)
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delay_mu(self.t_frame)
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@ -274,9 +277,12 @@ class Fastino:
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def apply_cic(self, channel_mask):
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"""Apply the staged interpolator configuration on the specified channels.
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Each Fastino channel includes a fourth order (cubic) CIC interpolator with
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variable rate change and variable output gain compensation (see
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:meth:`stage_cic`).
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Each Fastino channel starting with gateware v0.2 includes a fourth order
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(cubic) CIC interpolator with variable rate change and variable output
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gain compensation (see :meth:`stage_cic`).
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Fastino gateware before v0.2 does not include the interpolators and the
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methods affecting the CICs should not be used.
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Channels using non-unity interpolation rate should have
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continous DAC updates enabled (see :meth:`set_continuous`) unless
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