mirror of https://github.com/m-labs/artiq.git
469 lines
17 KiB
Python
469 lines
17 KiB
Python
from functools import reduce
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from operator import and_
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from migen import *
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from migen.genlib.record import Record
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from migen.genlib.cdc import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio import rtlink
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class _GrayCodeTransfer(Module):
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def __init__(self, width):
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self.i = Signal(width) # in rio domain
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self.o = Signal(width) # in rsys domain
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# # #
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# convert to Gray code
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value_gray_rio = Signal(width)
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self.sync.rio += value_gray_rio.eq(self.i ^ self.i[1:])
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# transfer to system clock domain
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value_gray_sys = Signal(width)
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self.specials += [
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NoRetiming(value_gray_rio),
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MultiReg(value_gray_rio, value_gray_sys, "rsys")
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]
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# convert back to binary
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value_sys = Signal(width)
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self.comb += value_sys[-1].eq(value_gray_sys[-1])
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for i in reversed(range(width-1)):
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self.comb += value_sys[i].eq(value_sys[i+1] ^ value_gray_sys[i])
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self.sync.rsys += self.o.eq(value_sys)
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class _RTIOCounter(Module):
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def __init__(self, width):
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self.width = width
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# Timestamp counter in RTIO domain
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self.value_rio = Signal(width)
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# Timestamp counter resynchronized to sys domain
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# Lags behind value_rio, monotonic and glitch-free
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self.value_sys = Signal(width)
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# # #
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# note: counter is in rtio domain and never affected by the reset CSRs
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self.sync.rtio += self.value_rio.eq(self.value_rio + 1)
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gt = _GrayCodeTransfer(width)
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self.submodules += gt
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self.comb += gt.i.eq(self.value_rio), self.value_sys.eq(gt.o)
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# CHOOSING A GUARD TIME
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#
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# The buffer must be transferred to the FIFO soon enough to account for:
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# * transfer of counter to sys domain: Tio + 2*Tsys + Tsys
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# * FIFO latency: Tsys + 2*Tio
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# * FIFO buffer latency: Tio
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# Therefore we must choose:
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# guard_io_cycles > (4*Tio + 4*Tsys)/Tio
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#
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# We are writing to the FIFO from the buffer when the guard time has been
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# reached. This can fill the FIFO and deassert the writable flag. A race
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# condition occurs that causes problems if the deassertion happens between
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# the CPU checking the writable flag (and reading 1) and writing a new event.
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#
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# When the FIFO is about to be full, it contains fifo_depth-1 events of
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# strictly increasing timestamps.
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#
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# Thus the FIFO-filling event's timestamp must satisfy:
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# timestamp*Tio > (fifo_depth-1)*Tio + time
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# We also have (guard time reached):
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# timestamp*Tio < time + guard_io_cycles*Tio
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# [NB: time > counter.value_sys*Tio]
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# Thus we must have:
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# guard_io_cycles > fifo_depth-1
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#
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# We can prevent overflows by choosing instead:
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# guard_io_cycles < fifo_depth-1
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class _OutputManager(Module):
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def __init__(self, interface, counter, fifo_depth, guard_io_cycles):
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data_width = rtlink.get_data_width(interface)
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address_width = rtlink.get_address_width(interface)
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fine_ts_width = rtlink.get_fine_ts_width(interface)
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ev_layout = []
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if data_width:
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ev_layout.append(("data", data_width))
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if address_width:
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ev_layout.append(("address", address_width))
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ev_layout.append(("timestamp", counter.width + fine_ts_width))
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# ev must be valid 1 cycle before we to account for the latency in
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# generating replace, sequence_error and nop
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self.ev = Record(ev_layout)
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self.writable = Signal()
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self.we = Signal() # maximum throughput 1/2
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self.underflow = Signal() # valid 1 cycle after we, pulsed
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self.sequence_error = Signal()
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self.collision_error = Signal()
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# # #
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# FIFO
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fifo = ClockDomainsRenamer({"write": "rsys", "read": "rio"})(
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AsyncFIFO(layout_len(ev_layout), fifo_depth))
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self.submodules += fifo
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fifo_in = Record(ev_layout)
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fifo_out = Record(ev_layout)
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self.comb += [
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fifo.din.eq(fifo_in.raw_bits()),
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fifo_out.raw_bits().eq(fifo.dout)
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]
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# Buffer
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buf_pending = Signal()
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buf = Record(ev_layout)
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buf_just_written = Signal()
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# Special cases
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replace = Signal()
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sequence_error = Signal()
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collision_error = Signal()
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any_error = Signal()
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nop = Signal()
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self.sync.rsys += [
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# Note: replace does not perform any RTLink address checks,
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# i.e. a write to a different address will be silently replaced
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# as well.
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replace.eq(self.ev.timestamp == buf.timestamp),
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# Detect sequence errors on coarse timestamps only
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# so that they are mutually exclusive with collision errors.
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sequence_error.eq(self.ev.timestamp[fine_ts_width:]
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< buf.timestamp[fine_ts_width:])
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]
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if fine_ts_width:
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self.sync.rsys += collision_error.eq(
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(self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
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& (self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width]))
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self.comb += any_error.eq(sequence_error | collision_error)
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if interface.suppress_nop:
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# disable NOP at reset: do not suppress a first write with all 0s
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nop_en = Signal(reset=0)
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addresses_equal = [getattr(self.ev, a) == getattr(buf, a)
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for a in ("data", "address")
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if hasattr(self.ev, a)]
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if addresses_equal:
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self.sync.rsys += nop.eq(
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nop_en & reduce(and_, addresses_equal))
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else:
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self.comb.eq(nop.eq(0))
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self.sync.rsys += [
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# buf now contains valid data. enable NOP.
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If(self.we & ~any_error, nop_en.eq(1)),
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# underflows cancel the write. allow it to be retried.
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If(self.underflow, nop_en.eq(0))
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]
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self.comb += [
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self.sequence_error.eq(self.we & sequence_error),
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self.collision_error.eq(self.we & collision_error)
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]
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# Buffer read and FIFO write
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self.comb += fifo_in.eq(buf)
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in_guard_time = Signal()
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self.comb += in_guard_time.eq(
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buf.timestamp[fine_ts_width:]
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< counter.value_sys + guard_io_cycles)
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self.sync.rsys += If(in_guard_time, buf_pending.eq(0))
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self.comb += \
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If(buf_pending,
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If(in_guard_time,
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If(buf_just_written,
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self.underflow.eq(1)
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).Else(
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fifo.we.eq(1)
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)
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),
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If(self.we & ~replace & ~nop & ~any_error,
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fifo.we.eq(1)
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)
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)
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# Buffer write
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# Must come after read to handle concurrent read+write properly
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self.sync.rsys += [
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buf_just_written.eq(0),
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If(self.we & ~nop & ~any_error,
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buf_just_written.eq(1),
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buf_pending.eq(1),
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buf.eq(self.ev)
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)
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]
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self.comb += self.writable.eq(fifo.writable)
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# Buffer output of FIFO to improve timing
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dout_stb = Signal()
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dout_ack = Signal()
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dout = Record(ev_layout)
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self.sync.rio += \
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If(fifo.re,
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dout_stb.eq(1),
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dout.eq(fifo_out)
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).Elif(dout_ack,
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dout_stb.eq(0)
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)
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self.comb += fifo.re.eq(fifo.readable & (~dout_stb | dout_ack))
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# FIFO read through buffer
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# TODO: report error on stb & busy
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self.comb += [
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dout_ack.eq(
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dout.timestamp[fine_ts_width:] == counter.value_rio),
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interface.stb.eq(dout_stb & dout_ack)
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]
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if data_width:
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self.comb += interface.data.eq(dout.data)
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if address_width:
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self.comb += interface.address.eq(dout.address)
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if fine_ts_width:
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self.comb += interface.fine_ts.eq(dout.timestamp[:fine_ts_width])
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class _InputManager(Module):
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def __init__(self, interface, counter, fifo_depth):
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data_width = rtlink.get_data_width(interface)
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fine_ts_width = rtlink.get_fine_ts_width(interface)
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ev_layout = []
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if data_width:
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ev_layout.append(("data", data_width))
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if interface.timestamped:
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ev_layout.append(("timestamp", counter.width + fine_ts_width))
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self.ev = Record(ev_layout)
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self.readable = Signal()
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self.re = Signal()
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self.overflow = Signal() # pulsed
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# # #
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fifo = ClockDomainsRenamer({"read": "rsys", "write": "rio"})(
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AsyncFIFO(layout_len(ev_layout), fifo_depth))
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self.submodules += fifo
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fifo_in = Record(ev_layout)
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fifo_out = Record(ev_layout)
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self.comb += [
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fifo.din.eq(fifo_in.raw_bits()),
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fifo_out.raw_bits().eq(fifo.dout)
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]
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# FIFO write
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if data_width:
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self.comb += fifo_in.data.eq(interface.data)
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if interface.timestamped:
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if fine_ts_width:
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full_ts = Cat(interface.fine_ts, counter.value_rio)
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else:
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full_ts = counter.value_rio
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self.comb += fifo_in.timestamp.eq(full_ts)
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self.comb += fifo.we.eq(interface.stb)
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# FIFO read
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self.comb += [
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self.ev.eq(fifo_out),
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self.readable.eq(fifo.readable),
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fifo.re.eq(self.re)
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]
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overflow_sync = PulseSynchronizer("rio", "rsys")
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overflow_ack_sync = PulseSynchronizer("rsys", "rio")
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self.submodules += overflow_sync, overflow_ack_sync
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overflow_blind = Signal()
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self.comb += overflow_sync.i.eq(fifo.we & ~fifo.writable & ~overflow_blind)
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self.sync.rio += [
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If(fifo.we & ~fifo.writable, overflow_blind.eq(1)),
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If(overflow_ack_sync.o, overflow_blind.eq(0))
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]
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self.comb += [
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overflow_ack_sync.i.eq(overflow_sync.o),
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self.overflow.eq(overflow_sync.o)
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]
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class Channel:
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def __init__(self, interface, probes=[], overrides=[],
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ofifo_depth=64, ififo_depth=64):
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self.interface = interface
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self.probes = probes
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self.overrides = overrides
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self.ofifo_depth = ofifo_depth
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self.ififo_depth = ififo_depth
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@classmethod
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def from_phy(cls, phy, **kwargs):
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probes = getattr(phy, "probes", [])
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overrides = getattr(phy, "overrides", [])
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return cls(phy.rtlink, probes, overrides, **kwargs)
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class _KernelCSRs(AutoCSR):
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def __init__(self, chan_sel_width,
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data_width, address_width, full_ts_width):
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self.reset = CSRStorage(reset=1)
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self.reset_phy = CSRStorage(reset=1)
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self.chan_sel = CSRStorage(chan_sel_width)
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if data_width:
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self.o_data = CSRStorage(data_width)
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if address_width:
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self.o_address = CSRStorage(address_width)
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self.o_timestamp = CSRStorage(full_ts_width)
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self.o_we = CSR()
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self.o_status = CSRStatus(4)
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self.o_underflow_reset = CSR()
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self.o_sequence_error_reset = CSR()
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self.o_collision_error_reset = CSR()
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if data_width:
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self.i_data = CSRStatus(data_width)
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self.i_timestamp = CSRStatus(full_ts_width)
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self.i_re = CSR()
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self.i_status = CSRStatus(2)
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self.i_overflow_reset = CSR()
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self.counter = CSRStatus(full_ts_width)
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self.counter_update = CSR()
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class RTIO(Module):
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def __init__(self, channels, full_ts_width=63, guard_io_cycles=20):
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data_width = max(rtlink.get_data_width(c.interface)
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for c in channels)
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address_width = max(rtlink.get_address_width(c.interface)
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for c in channels)
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fine_ts_width = max(rtlink.get_fine_ts_width(c.interface)
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for c in channels)
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self.data_width = data_width
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self.address_width = address_width
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self.fine_ts_width = fine_ts_width
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# CSRs
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self.kcsrs = _KernelCSRs(bits_for(len(channels)-1),
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data_width, address_width,
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full_ts_width)
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# Clocking/Reset
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# Create rsys, rio and rio_phy domains based on sys and rtio
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# with reset controlled by CSR.
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self.clock_domains.cd_rsys = ClockDomain()
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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self.comb += [
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self.cd_rsys.clk.eq(ClockSignal()),
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self.cd_rsys.rst.eq(self.kcsrs.reset.storage)
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]
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self.comb += self.cd_rio.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio,
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self.kcsrs.reset.storage | ResetSignal("rtio",
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allow_reset_less=True))
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self.comb += self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio_phy,
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self.kcsrs.reset_phy.storage | ResetSignal("rtio",
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allow_reset_less=True))
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# Managers
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self.submodules.counter = _RTIOCounter(full_ts_width - fine_ts_width)
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i_datas, i_timestamps = [], []
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o_statuses, i_statuses = [], []
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sel = self.kcsrs.chan_sel.storage
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for n, channel in enumerate(channels):
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selected = Signal()
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self.comb += selected.eq(sel == n)
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o_manager = _OutputManager(channel.interface.o, self.counter,
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channel.ofifo_depth, guard_io_cycles)
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self.submodules += o_manager
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if hasattr(o_manager.ev, "data"):
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self.comb += o_manager.ev.data.eq(
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self.kcsrs.o_data.storage)
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if hasattr(o_manager.ev, "address"):
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self.comb += o_manager.ev.address.eq(
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self.kcsrs.o_address.storage)
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ts_shift = (len(self.kcsrs.o_timestamp.storage)
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- len(o_manager.ev.timestamp))
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self.comb += o_manager.ev.timestamp.eq(
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self.kcsrs.o_timestamp.storage[ts_shift:])
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self.comb += o_manager.we.eq(selected & self.kcsrs.o_we.re)
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underflow = Signal()
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sequence_error = Signal()
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collision_error = Signal()
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self.sync.rsys += [
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If(selected & self.kcsrs.o_underflow_reset.re,
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underflow.eq(0)),
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If(selected & self.kcsrs.o_sequence_error_reset.re,
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sequence_error.eq(0)),
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If(selected & self.kcsrs.o_collision_error_reset.re,
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collision_error.eq(0)),
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If(o_manager.underflow, underflow.eq(1)),
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If(o_manager.sequence_error, sequence_error.eq(1)),
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If(o_manager.collision_error, collision_error.eq(1))
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]
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o_statuses.append(Cat(~o_manager.writable,
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underflow,
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sequence_error,
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collision_error))
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if channel.interface.i is not None:
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i_manager = _InputManager(channel.interface.i, self.counter,
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channel.ififo_depth)
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self.submodules += i_manager
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if hasattr(i_manager.ev, "data"):
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i_datas.append(i_manager.ev.data)
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else:
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i_datas.append(0)
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if channel.interface.i.timestamped:
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ts_shift = (len(self.kcsrs.i_timestamp.status)
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- len(i_manager.ev.timestamp))
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i_timestamps.append(i_manager.ev.timestamp << ts_shift)
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else:
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i_timestamps.append(0)
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self.comb += i_manager.re.eq(selected & self.kcsrs.i_re.re)
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overflow = Signal()
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self.sync.rsys += [
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If(selected & self.kcsrs.i_overflow_reset.re,
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overflow.eq(0)),
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If(i_manager.overflow,
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overflow.eq(1))
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]
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i_statuses.append(Cat(~i_manager.readable, overflow))
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else:
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i_datas.append(0)
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i_timestamps.append(0)
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i_statuses.append(0)
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if data_width:
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self.comb += self.kcsrs.i_data.status.eq(Array(i_datas)[sel])
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self.comb += [
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self.kcsrs.i_timestamp.status.eq(Array(i_timestamps)[sel]),
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self.kcsrs.o_status.status.eq(Array(o_statuses)[sel]),
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self.kcsrs.i_status.status.eq(Array(i_statuses)[sel])
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]
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# Counter access
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self.sync += \
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If(self.kcsrs.counter_update.re,
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self.kcsrs.counter.status.eq(self.counter.value_sys
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<< fine_ts_width)
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)
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def get_csrs(self):
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return self.kcsrs.get_csrs()
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