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d6157514c7
artiq/artiq/gateware/drtio/transceiver
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Sebastien Bourdeauducq d6157514c7 gtp_7series: flexible QPLL channel selection
2018-01-23 12:03:09 +08:00
..
__init__.py drtio: GTX WIP 2016-10-14 00:36:13 +08:00
clock_aligner.py add artix7 gtp (3gbps), share clock aligner with gth_ultrascale 2018-01-19 12:17:54 +01:00
gth_ultrascale_init.py add artix7 gtp (3gbps), share clock aligner with gth_ultrascale 2018-01-19 12:17:54 +01:00
gth_ultrascale.py sayma,kasli: use new pin names 2018-01-22 11:51:07 +08:00
gtp_7series_init.py add artix7 gtp (3gbps), share clock aligner with gth_ultrascale 2018-01-19 12:17:54 +01:00
gtp_7series.py gtp_7series: flexible QPLL channel selection 2018-01-23 12:03:09 +08:00