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artiq/artiq/examples
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Sebastien Bourdeauducq 262cd62544 examples/blink_forever: port to NAC3
2021-11-10 13:59:59 +08:00
..
kasli turn kasli_tester into a frontend tool 2020-01-21 16:13:04 +08:00
kasli_drtioswitching examples: use default IP addresses for boards 2019-10-16 16:18:30 +08:00
kasli_sawgmaster examples/sines_urukul_sayma: adapt for sayma v2, use 1 DAC only 2020-04-05 16:51:40 +08:00
kasli_suservo suservo: extract boilerplate 2018-06-01 15:37:07 +00:00
kc705_nist_clock examples/blink_forever: port to NAC3 2021-11-10 13:59:59 +08:00
metlino_sayma_ttl metlino_sayma_ttl: Fix RTIO frequency & demo code (#1516) 2020-09-03 15:08:31 +08:00
no_hardware use sipyco (#585) 2019-11-10 15:55:17 +08:00
sayma_master examples/sayma_master: update device_db 2019-10-16 18:49:25 +08:00
artiq_ipython_notebook.ipynb fix device_db alias corner case bugs. Closes #1140 2019-11-14 16:22:45 +08:00
fit_image.py ship examples with package 2016-04-05 13:59:39 +08:00
README.rst examples: Add README 2019-12-17 13:35:19 +00:00
remote_exec_controller.py use sipyco (#585) 2019-11-10 15:55:17 +08:00

README.rst 

ARTIQ experiment examples
=========================

This directory contains several sample ARTIQ master configurations
and associated experiments that illustrate basic usage of various
hardware and software features.

New users might want to peruse the ``no_hardware`` directory to
explore the argument/dataset machinery without needing access to
hardware, and the ``kc705_nist_clock`` directory for inspiration
on how to coordinate between host and FPGA core device code.