mirror of https://github.com/m-labs/artiq.git
84 lines
3.4 KiB
Python
84 lines
3.4 KiB
Python
from migen import *
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from migen.genlib.io import DifferentialOutput, DifferentialInput, DDROutput
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class SamplerPads(Module):
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def __init__(self, platform, eem):
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self.sck_en = Signal()
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self.cnv = Signal()
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self.clkout = Signal()
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spip = platform.request("{}_adc_spi_p".format(eem))
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spin = platform.request("{}_adc_spi_n".format(eem))
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cnv = platform.request("{}_cnv".format(eem))
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sdr = platform.request("{}_sdr".format(eem))
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dp = platform.request("{}_adc_data_p".format(eem))
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dn = platform.request("{}_adc_data_n".format(eem))
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clkout_se = Signal()
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clkout_inv = Signal()
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sck = Signal()
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self.specials += [
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DifferentialOutput(self.cnv, cnv.p, cnv.n),
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DifferentialOutput(1, sdr.p, sdr.n),
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DDROutput(self.sck_en, 0, sck, ClockSignal("rio_phy")),
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DifferentialOutput(sck, spip.clk, spin.clk),
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DifferentialInput(dp.clkout, dn.clkout, clkout_se),
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# FIXME (hardware): CLKOUT is inverted
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# (Sampler v2.0, v2.1) out on rising, in on falling
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Instance("BUFR", i_I=clkout_se, o_O=clkout_inv)
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]
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self.comb += self.clkout.eq(~clkout_inv)
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# define clock here before the input delays below
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self.clkout_p = dp.clkout # available for false paths
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platform.add_platform_command(
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"create_clock -name {clk} -period 8 [get_nets {clk}]",
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clk=dp.clkout)
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# platform.add_period_constraint(sampler_pads.clkout_p, 8.)
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for i in "abcd":
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sdo = Signal()
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setattr(self, "sdo{}".format(i), sdo)
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if i != "a":
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# FIXME (hardware): sdob, sdoc, sdod are inverted
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# (Sampler v2.0, v2.1)
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sdo, sdo_inv = Signal(), sdo
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self.comb += sdo_inv.eq(~sdo)
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sdop = getattr(dp, "sdo{}".format(i))
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sdon = getattr(dn, "sdo{}".format(i))
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self.specials += [
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DifferentialInput(sdop, sdon, sdo),
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]
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# -0+1.5 hold (t_HSDO_SDR), -0.5+0.5 skew
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platform.add_platform_command(
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"set_input_delay -clock {clk} -max 2 [get_ports {port}]\n"
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"set_input_delay -clock {clk} -min -0.5 [get_ports {port}]",
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clk=dp.clkout, port=sdop)
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class UrukulPads(Module):
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def __init__(self, platform, *eems):
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spip, spin = [[
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platform.request("{}_qspi_{}".format(eem, pol), 0)
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for eem in eems] for pol in "pn"]
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ioup = [platform.request("{}_io_update".format(eem), 0)
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for eem in eems]
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self.cs_n = Signal()
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self.clk = Signal()
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self.io_update = Signal()
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self.specials += [(
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DifferentialOutput(~self.cs_n, spip[i].cs, spin[i].cs),
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DifferentialOutput(self.clk, spip[i].clk, spin[i].clk),
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DifferentialOutput(self.io_update, ioup[i].p, ioup[i].n))
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for i in range(len(eems))]
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for i in range(8):
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mosi = Signal()
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setattr(self, "mosi{}".format(i), mosi)
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for i in range(4*len(eems)):
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self.specials += [
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DifferentialOutput(getattr(self, "mosi{}".format(i)),
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getattr(spip[i // 4], "mosi{}".format(i % 4)),
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getattr(spin[i // 4], "mosi{}".format(i % 4)))
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]
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