mirror of https://github.com/m-labs/artiq.git
48 lines
1.7 KiB
Python
48 lines
1.7 KiB
Python
from migen import *
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from migen.build.platforms.sinara import kasli
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from misoc.interconnect.csr import *
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from misoc.interconnect import wishbone
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from misoc.cores import vexriscv
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from misoc.integration.wb_slaves import WishboneSlaveManager
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class KernelCPU(Module):
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def __init__(self, platform,
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exec_address=0x45000000,
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main_mem_origin=0x40000000,
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l2_size=8192):
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self._reset = CSRStorage(reset=1)
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# # #
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# CPU core
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self.clock_domains.cd_sys_kernel = ClockDomain()
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self.comb += [
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self.cd_sys_kernel.clk.eq(ClockSignal()),
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self.cd_sys_kernel.rst.eq(self._reset.storage)
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]
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kasli_v1 = isinstance(platform, kasli.Platform) and platform.hw_rev in ("v1.0", "v1.1")
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self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(
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vexriscv.VexRiscv(platform, exec_address,
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variant="VexRiscv_IMA" if kasli_v1 else "VexRiscv_G"))
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self.cpu_dw = len(self.cpu.dbus.dat_w)
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self._wb_slaves = WishboneSlaveManager(0x80000000, dw=self.cpu_dw)
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# DRAM access
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self.wb_sdram = wishbone.Interface(data_width=self.cpu_dw, adr_width=32-log2_int(self.cpu_dw//8))
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self.add_wb_slave(main_mem_origin, 0x10000000, self.wb_sdram)
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def get_csrs(self):
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return [self._reset]
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def do_finalize(self):
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self.submodules.wishbonecon = wishbone.InterconnectShared(
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[self.cpu.ibus, self.cpu.dbus],
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self._wb_slaves.get_interconnect_slaves(), register=True, dw=self.cpu_dw)
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def add_wb_slave(self, origin, length, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_slaves.add(origin, length, interface)
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