19 Commits

Author	SHA1	Message	Date
occheung	cb247f235f	gateware: pass adr_w/data_w to submodules	2021-11-08 16:59:08 +08:00
occheung	90f944481c	kernel_cpu: add fpu if not kasli v1.x	2021-11-08 16:59:08 +08:00
occheung	fc42d053d9	kernel: use vexriscv	2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq	92fd705990	increase memory allocated to comms CPU ... See discussion in #1612.	2021-02-21 19:06:12 +08:00
Robert Jördens	529033e016	kernel_cpu: disable PCU ... * contributes to long timing paths on artix 7 (kasli) * currently only used for testing and debugging	2018-01-12 12:03:50 +00:00
Sebastien Bourdeauducq	4deb5f6a45	gateware: use new MiSoC Wishbone address system	2017-07-13 19:16:49 +08:00
Robert Jördens	c022b53578	kernel_cpu: enable perf counters	2017-02-18 14:09:12 +01:00
whitequark	898a716b91	runtime: work around mor1kx ignoring low bits of reset address. ... Fixes #599.	2016-10-31 18:13:15 +00:00
whitequark	617e345d16	gateware: fix kernel CPU exec address.	2016-10-31 15:16:35 +00:00
whitequark	2ac85cd40f	runtime: implement prototype background RPCs.	2016-10-29 21:34:25 +00:00
whitequark	b52ecda1d5	runtime: make memory map saner.	2016-10-06 18:05:38 +00:00
whitequark	9366a29483	Implement core device storage (fixes #219).	2016-01-10 13:04:55 +00:00
whitequark	577108554f	Move kernel CPU address space up to 0x40800000.	2016-01-07 18:26:11 +00:00
Sebastien Bourdeauducq	e26147b2ac	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
Florent Kermarrec	38a0f63bd2	gateware/soc: use Minicon SDRAM controller and 128KB shared L2 cache	2015-06-18 12:18:03 +02:00
Sebastien Bourdeauducq	e4251c7f41	runtime: get lwip to run	2015-04-22 15:01:32 +08:00
Sebastien Bourdeauducq	1ed60e0829	gateware/amp: use new ModuleTransformer API	2015-04-06 23:54:53 +08:00
Sebastien Bourdeauducq	c6d3750076	runtime,amp: set kernel memory start to SDRAM+128K, use custom linker file to split memory	2015-04-03 16:03:38 +08:00
Sebastien Bourdeauducq	5bd8d414cf	gateware/amp: add kernel CPU and mailbox modules	2015-04-02 16:49:36 +08:00