2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-26 03:38:25 +08:00
artiq/soc/targets
2015-06-18 09:49:52 -06:00
..
artiq_kc705.py gateware/soc: use Minicon SDRAM controller and 128KB shared L2 cache 2015-06-18 12:18:03 +02:00
artiq_pipistrello.py pipistrello: smaller L2 cache 2015-06-18 09:49:52 -06:00