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artiq
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pipistrello: smaller L2 cache

This commit is contained in:
Sébastien Bourdeauducq 2015-06-18 09:49:52 -06:00
parent 77ca8bbf0f
commit 3636025e69
1 changed files with 1 additions and 1 deletions
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soc/targets/artiq_pipistrello.py
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@ -71,7 +71,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
def __init__(self, platform, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self, platform,
cpu_type=cpu_type,
sdram_controller_settings=MiniconSettings(l2_size=128*1024),
sdram_controller_settings=MiniconSettings(l2_size=64*1024),
with_timer=False, **kwargs)
AMPSoC.__init__(self)
platform.toolchain.ise_commands += """