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pipistrello: smaller L2 cache
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@ -71,7 +71,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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BaseSoC.__init__(self, platform,
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cpu_type=cpu_type,
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sdram_controller_settings=MiniconSettings(l2_size=128*1024),
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sdram_controller_settings=MiniconSettings(l2_size=64*1024),
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with_timer=False, **kwargs)
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AMPSoC.__init__(self)
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platform.toolchain.ise_commands += """
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