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78 lines
3.2 KiB
Python
78 lines
3.2 KiB
Python
from types import SimpleNamespace
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from migen import *
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from artiq.gateware.drtio import link_layer, rt_packets, iot, rt_controller, aux_controller
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class DRTIOSatellite(Module):
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def __init__(self, transceiver, rx_synchronizer, channels, fine_ts_width=3, full_ts_width=63,
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ll_rx_ready_confirm=1000):
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self.submodules.link_layer = link_layer.LinkLayer(
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transceiver.encoder, transceiver.decoders, ll_rx_ready_confirm)
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self.comb += [
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transceiver.rx_reset.eq(self.link_layer.rx_reset),
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self.link_layer.rx_ready.eq(transceiver.rx_ready)
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]
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link_layer_sync = SimpleNamespace(
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tx_aux_frame=self.link_layer.tx_aux_frame,
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tx_aux_data=self.link_layer.tx_aux_data,
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tx_aux_ack=self.link_layer.tx_aux_ack,
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tx_rt_frame=self.link_layer.tx_rt_frame,
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tx_rt_data=self.link_layer.tx_rt_data,
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rx_aux_stb=rx_synchronizer.resync(self.link_layer.rx_aux_stb),
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rx_aux_frame=rx_synchronizer.resync(self.link_layer.rx_aux_frame),
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rx_aux_data=rx_synchronizer.resync(self.link_layer.rx_aux_data),
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rx_rt_frame=rx_synchronizer.resync(self.link_layer.rx_rt_frame),
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rx_rt_data=rx_synchronizer.resync(self.link_layer.rx_rt_data)
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)
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self.submodules.rt_packets = ClockDomainsRenamer("rtio")(
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rt_packets.RTPacketSatellite(link_layer_sync))
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self.submodules.iot = ClockDomainsRenamer("rtio")(
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iot.IOT(self.rt_packets, channels, fine_ts_width, full_ts_width))
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# TODO: remote resets
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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self.comb += [
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self.cd_rio.clk.eq(ClockSignal("rtio")),
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self.cd_rio.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
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self.cd_rio_phy.clk.eq(ClockSignal("rtio")),
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self.cd_rio_phy.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
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]
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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def get_csrs(self):
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return self.aux_controller.get_csrs()
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class DRTIOMaster(Module):
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def __init__(self, transceiver, channel_count=1024, fine_ts_width=3, ll_rx_ready_confirm=1000):
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self.submodules.link_layer = link_layer.LinkLayer(
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transceiver.encoder, transceiver.decoders, ll_rx_ready_confirm)
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self.comb += [
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transceiver.rx_reset.eq(self.link_layer.rx_reset),
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self.link_layer.rx_ready.eq(transceiver.rx_ready)
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]
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self.submodules.rt_packets = rt_packets.RTPacketMaster(self.link_layer)
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self.submodules.rt_controller = rt_controller.RTController(
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self.rt_packets, channel_count, fine_ts_width)
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self.submodules.rt_manager = rt_controller.RTManager(self.rt_packets)
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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def get_kernel_csrs(self):
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return self.rt_controller.get_kernel_csrs()
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def get_csrs(self):
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return (self.link_layer.get_csrs() +
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self.rt_controller.get_csrs() +
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self.rt_manager.get_csrs() +
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self.aux_controller.get_csrs())
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