Sebastien Bourdeauducq 04b0db1a91 targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance		2015-12-29 17:00:57 +08:00
..
amp	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
rtio	gateware/rtio: add LogChannel	2015-12-26 22:43:28 +08:00
targets	targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance	2015-12-29 17:00:57 +08:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9xxx.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_qc1.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
nist_qc2.py	gateware,runtime: use new migen/misoc	2015-11-04 00:35:03 +08:00
soc.py	gateware/soc: use new SDRAM API call	2015-12-16 14:59:35 +08:00