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https://github.com/m-labs/artiq.git
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Sebastien Bourdeauducq
938e1c2842
The only advantage of UP is to support the Papilio Pro, but that port is also very limited in other ways and the Pipistrello provides a more reasonable platform that also supports AMP. On the other hand, RPCs on UP are difficult to implement with the session.c protocol system (without an operating system or coroutines), along with many other minor difficulties and maintainance issues. Planned features such as watchdogs in the core device are also difficult on UP.
33 lines
1.3 KiB
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33 lines
1.3 KiB
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FPGA board ports
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KC705
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The main target board for the ARTIQ core device is the KC705 development board from Xilinx.
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Pipistrello
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The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alternative.
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When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are mapped to RTIO channels as follows:
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+--------------+----------+-----------------+
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| RTIO channel | TTL line | Capability |
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+==============+==========+=================+
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| 0 | PMT0 | Input only |
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+--------------+----------+-----------------+
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| 1 | PMT1 | Input only |
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+--------------+----------+-----------------+
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| 2-18 | TTL0-16 | Output only |
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+--------------+----------+-----------------+
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| 19-21 | LEDs | Output only |
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+--------------+----------+-----------------+
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| 22 | TTL2 | Output only |
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+--------------+----------+-----------------+
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The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention.
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The board can accept an external RTIO clock connected to PMT2.
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