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artiq/artiq/compiler
whitequark 3fbee2707b analyses.domination: consider unreachable blocks dominated by any other.
As a result, the dominator tree can now process arbitrary (reducible)
CFGs and we do not run DCE before analyses, risking loss of
correspondence to the AST, which would arbitrarily silence analyses.
2015-12-18 16:39:52 +08:00
..
algorithms transforms.interleaver: unroll loops. 2015-12-17 00:52:22 +08:00
analyses analyses.domination: consider unreachable blocks dominated by any other. 2015-12-18 16:39:52 +08:00
testbench compiler: explicitly represent loops in IR. 2015-12-16 15:33:26 +08:00
transforms transforms.interleaver: unroll loops. 2015-12-17 00:52:22 +08:00
validators validators.escape: don't fail on quoted values in lhs. 2015-12-16 13:57:02 +08:00
__init__.py compiler: pull in dependencies in more finely grained way (fixes #181). 2015-11-24 17:32:04 +08:00
asttyped.py compiler: explicitly represent loops in IR. 2015-12-16 15:33:26 +08:00
builtins.py compiler: implement 'with watchdog' support. 2015-12-10 23:11:00 +08:00
embedding.py compiler: refactor to use builtins.TInt{32,64}. (NFC) 2015-12-10 23:06:23 +08:00
iodelay.py compiler.iodelay: correctly fold max(0, [0, ]...). 2015-11-24 00:46:55 +08:00
ir.py transforms.interleaver: unroll loops. 2015-12-17 00:52:22 +08:00
module.py analyses.domination: consider unreachable blocks dominated by any other. 2015-12-18 16:39:52 +08:00
prelude.py compiler: implement 'with watchdog' support. 2015-12-10 23:11:00 +08:00
targets.py compiler: make IR dumps vastly more readable. 2015-11-17 00:23:34 +03:00
types.py compiler: fix tests. 2015-12-10 23:16:36 +08:00