analyses.domination: consider unreachable blocks dominated by any other.

As a result, the dominator tree can now process arbitrary (reducible)
CFGs and we do not run DCE before analyses, risking loss of
correspondence to the AST, which would arbitrarily silence analyses.

artiq/compiler/analyses/domination.py

@@ -74,7 +74,11 @@ class GenericDominatorTree:
         return self._block_of_name[self._doms[self._name_of_block[block]]]
 
     def dominators(self, block):
-        yield block
+        # Blocks that are statically unreachable from entry are considered
+        # dominated by every other block.
+        if block not in self._name_of_block:
+            yield from self._block_of_name
+            return
 
         block_name = self._name_of_block[block]
         while block_name != self._doms[block_name]:
@@ -103,7 +107,9 @@ class DominatorTree(GenericDominatorTree):
 
     def _prev_block_names(self, block_name):
         for block in self._block_of_name[block_name].predecessors():
-            yield self._name_of_block[block]
+            # Only return predecessors that are statically reachable from entry.
+            if block in self._name_of_block:
+                yield self._name_of_block[block]
 
 class PostDominatorTree(GenericDominatorTree):
     def __init__(self, function):

artiq/compiler/module.py

@@ -70,10 +70,9 @@ class Module:
         devirtualization.visit(src.typedtree)
         self.artiq_ir = artiq_ir_generator.visit(src.typedtree)
         artiq_ir_generator.annotate_calls(devirtualization)
-        dead_code_eliminator.process(self.artiq_ir)
         local_access_validator.process(self.artiq_ir)
-        interleaver.process(self.artiq_ir)
         dead_code_eliminator.process(self.artiq_ir)
+        interleaver.process(self.artiq_ir)
 
     def build_llvm_ir(self, target):
         """Compile the module to LLVM IR for the specified target."""