mirror of https://github.com/m-labs/artiq
716 lines
29 KiB
Python
Executable File
716 lines
29 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen.genlib.io import DifferentialOutput
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.cores.a7_gtp import *
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from misoc.targets.kasli import (
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BaseSoC, MiniSoC, soc_kasli_args, soc_kasli_argdict)
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
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from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path
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from artiq.gateware import eem
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.wrpll import WRPLL, DDMTDSamplerGTP
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform):
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self.pll_reset = CSRStorage(reset=1)
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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if platform.hw_rev == "v2.0":
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clk_synth = platform.request("cdr_clk_clean_fabric")
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else:
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clk_synth = platform.request("si5324_clkout_fabric")
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clk_synth_se = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
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]
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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fb_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN2=clk_synth_se,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=0,
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# VCO @ 1.5GHz when using 125MHz input
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p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=fb_clk,
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i_RST=self.pll_reset.storage,
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o_CLKFBOUT=fb_clk,
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p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=rtio_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self.pll_locked.status)
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]
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class SMAClkinForward(Module):
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def __init__(self, platform):
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sma_clkin = platform.request("sma_clkin")
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sma_clkin_se = Signal()
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sma_clkin_buffered = Signal()
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cdr_clk_se = Signal()
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cdr_clk = platform.request("cdr_clk")
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self.specials += [
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Instance("IBUFDS", i_I=sma_clkin.p, i_IB=sma_clkin.n, o_O=sma_clkin_se),
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Instance("BUFIO", i_I=sma_clkin_se, o_O=sma_clkin_buffered),
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Instance("ODDR", i_C=sma_clkin_buffered, i_CE=1, i_D1=0, i_D2=1, o_Q=cdr_clk_se),
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Instance("OBUFDS", i_I=cdr_clk_se, o_O=cdr_clk.p, o_OB=cdr_clk.n)
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]
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class StandaloneBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, gateware_identifier_str=None, hw_rev="v2.0", **kwargs):
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if hw_rev in ("v1.0", "v1.1"):
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cpu_bus_width = 32
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else:
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cpu_bus_width = 64
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MiniSoC.__init__(self,
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cpu_type="vexriscv",
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hw_rev=hw_rev,
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cpu_bus_width=cpu_bus_width,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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if self.platform.hw_rev == "v2.0":
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self.submodules.error_led = gpio.GPIOOut(Cat(
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self.platform.request("error_led")))
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self.csr_devices.append("error_led")
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self.submodules += SMAClkinForward(self.platform)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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def add_rtio(self, rtio_channels, sed_lanes=8):
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self.submodules.rtio_crg = _RTIOCRG(self.platform)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(self.platform)
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if(), self.cpu_dw))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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# Only add MonInj core if there is anything to monitor
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if any([len(c.probes) for c in rtio_channels]):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.get_native_sdram_if(), cpu_dw=self.cpu_dw)
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self.csr_devices.append("rtio_analyzer")
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class Tester(StandaloneBase):
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"""
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Configuration for CI tests. Contains the maximum number of different EEMs.
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"""
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def __init__(self, hw_rev=None, dds=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v2.0"
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if dds is None:
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dds = "ad9910"
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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eem.DIO.add_std(self, 5,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X,
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edge_counter_cls=edge_counter.SimpleEdgeCounter)
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eem.Urukul.add_std(self, 0, 1, ttl_serdes_7series.Output_8X, dds,
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ttl_simple.ClockGen)
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eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
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eem.Zotino.add_std(self, 4, ttl_serdes_7series.Output_8X)
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if hw_rev in ("v1.0", "v1.1"):
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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class SUServo(StandaloneBase):
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"""
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SUServo (Sampler-Urukul-Servo) extension variant configuration
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"""
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v2.0"
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["SI5324_AS_SYNTHESIZER"] = None
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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# EEM0, EEM1: DIO
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eem.DIO.add_std(self, 0,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 1,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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# EEM3/2: Sampler, EEM5/4: Urukul, EEM7/6: Urukul
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eem.SUServo.add_std(self,
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eems_sampler=(3, 2),
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eems_urukul=[[5, 4], [7, 6]])
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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pads = self.platform.lookup_request("sampler3_adc_data_p")
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self.platform.add_false_path_constraints(
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pads.clkout, self.rtio_crg.cd_rtio.clk)
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self.platform.add_false_path_constraints(
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pads.clkout, self.crg.cd_sys.clk)
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class MasterBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"drtioaux": 0x50000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, hw_rev="v2.0", **kwargs):
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if hw_rev in ("v1.0", "v1.1"):
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cpu_bus_width = 32
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else:
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cpu_bus_width = 64
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MiniSoC.__init__(self,
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cpu_type="vexriscv",
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hw_rev=hw_rev,
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cpu_bus_width=cpu_bus_width,
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sdram_controller_type="minicon",
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l2_size=128*1024,
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integrated_sram_size=8192,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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platform = self.platform
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if platform.hw_rev == "v2.0":
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self.submodules.error_led = gpio.GPIOOut(Cat(
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self.platform.request("error_led")))
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self.csr_devices.append("error_led")
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self.submodules += SMAClkinForward(platform)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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drtio_data_pads = []
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if enable_sata:
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drtio_data_pads.append(platform.request("sata"))
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drtio_data_pads += [platform.request("sfp", i) for i in range(1, 3)]
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if self.platform.hw_rev == "v2.0":
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drtio_data_pads.append(platform.request("sfp", 3))
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if self.platform.hw_rev in ("v1.0", "v1.1"):
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sfp_ctls = [platform.request("sfp_ctl", i) for i in range(1, 3)]
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self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
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self.submodules.drtio_transceiver = gtp_7series.GTP(
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qpll_channel=self.drtio_qpll_channel,
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data_pads=drtio_data_pads,
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.sync += self.disable_cdr_clk_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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if enable_sata:
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sfp_channels = self.drtio_transceiver.channels[1:]
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else:
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sfp_channels = self.drtio_transceiver.channels
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if self.platform.hw_rev in ("v1.0", "v1.1"):
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self.comb += [sfp_ctl.led.eq(channel.rx_ready)
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for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)]
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if self.platform.hw_rev == "v2.0":
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self.comb += [self.virtual_leds.get(i + 1).eq(channel.rx_ready)
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for i, channel in enumerate(sfp_channels)]
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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drtio_csr_group = []
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drtioaux_csr_group = []
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drtioaux_memory_group = []
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self.drtio_cri = []
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for i in range(len(self.drtio_transceiver.channels)):
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core_name = "drtio" + str(i)
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coreaux_name = "drtioaux" + str(i)
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memory_name = "drtioaux" + str(i) + "_mem"
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drtio_csr_group.append(core_name)
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drtioaux_csr_group.append(coreaux_name)
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drtioaux_memory_group.append(memory_name)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
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core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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self.drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw))
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setattr(self.submodules, coreaux_name, coreaux)
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self.csr_devices.append(coreaux_name)
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memory_address = self.mem_map["drtioaux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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gtp = self.drtio_transceiver.gtps[0]
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platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gtp.txoutclk, gtp.rxoutclk)
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for gtp in self.drtio_transceiver.gtps[1:]:
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platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, gtp.rxoutclk)
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self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels, sed_lanes=8):
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# Only add MonInj core if there is anything to monitor
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if any([len(c.probes) for c in rtio_channels]):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if(), self.cpu_dw))
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self.register_kernel_cpu_csrdevice("rtio")
|
|
self.register_kernel_cpu_csrdevice("rtio_dma")
|
|
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
|
[self.rtio.cri, self.rtio_dma.cri],
|
|
[self.rtio_core.cri] + self.drtio_cri,
|
|
enable_routing=True)
|
|
self.register_kernel_cpu_csrdevice("cri_con")
|
|
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
|
|
self.csr_devices.append("routing_table")
|
|
|
|
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
|
|
self.get_native_sdram_if(), cpu_dw=self.cpu_dw)
|
|
self.csr_devices.append("rtio_analyzer")
|
|
|
|
# Never running out of stupid features, GTs on A7 make you pack
|
|
# unrelated transceiver PLLs into one GTPE2_COMMON yourself.
|
|
def create_qpll(self):
|
|
# The GTP acts up if you send any glitch to its
|
|
# clock input, even while the PLL is held in reset.
|
|
self.disable_cdr_clk_ibuf = Signal(reset=1)
|
|
self.disable_cdr_clk_ibuf.attr.add("no_retiming")
|
|
if self.platform.hw_rev == "v2.0":
|
|
cdr_clk_clean = self.platform.request("cdr_clk_clean")
|
|
else:
|
|
cdr_clk_clean = self.platform.request("si5324_clkout")
|
|
cdr_clk_clean_buf = Signal()
|
|
self.specials += Instance("IBUFDS_GTE2",
|
|
i_CEB=self.disable_cdr_clk_ibuf,
|
|
i_I=cdr_clk_clean.p, i_IB=cdr_clk_clean.n,
|
|
o_O=cdr_clk_clean_buf)
|
|
# Note precisely the rules Xilinx made up:
|
|
# refclksel=0b001 GTREFCLK0 selected
|
|
# refclksel=0b010 GTREFCLK1 selected
|
|
# but if only one clock is used, then it must be 001.
|
|
qpll_drtio_settings = QPLLSettings(
|
|
refclksel=0b001,
|
|
fbdiv=4,
|
|
fbdiv_45=5,
|
|
refclk_div=1)
|
|
qpll_eth_settings = QPLLSettings(
|
|
refclksel=0b010,
|
|
fbdiv=4,
|
|
fbdiv_45=5,
|
|
refclk_div=1)
|
|
qpll = QPLL(cdr_clk_clean_buf, qpll_drtio_settings,
|
|
self.crg.clk125_buf, qpll_eth_settings)
|
|
self.submodules += qpll
|
|
self.drtio_qpll_channel, self.ethphy_qpll_channel = qpll.channels
|
|
|
|
|
|
class SatelliteBase(BaseSoC):
|
|
mem_map = {
|
|
"drtioaux": 0x50000000,
|
|
}
|
|
mem_map.update(BaseSoC.mem_map)
|
|
|
|
def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, hw_rev="v2.0", **kwargs):
|
|
if hw_rev in ("v1.0", "v1.1"):
|
|
cpu_bus_width = 32
|
|
else:
|
|
cpu_bus_width = 64
|
|
BaseSoC.__init__(self,
|
|
cpu_type="vexriscv",
|
|
hw_rev=hw_rev,
|
|
cpu_bus_width=cpu_bus_width,
|
|
sdram_controller_type="minicon",
|
|
l2_size=128*1024,
|
|
**kwargs)
|
|
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
|
|
|
|
platform = self.platform
|
|
|
|
if self.platform.hw_rev == "v2.0":
|
|
self.submodules.error_led = gpio.GPIOOut(Cat(
|
|
self.platform.request("error_led")))
|
|
self.csr_devices.append("error_led")
|
|
|
|
disable_cdr_clk_ibuf = Signal(reset=1)
|
|
disable_cdr_clk_ibuf.attr.add("no_retiming")
|
|
if self.platform.hw_rev == "v2.0":
|
|
cdr_clk_clean = self.platform.request("cdr_clk_clean")
|
|
else:
|
|
cdr_clk_clean = self.platform.request("si5324_clkout")
|
|
cdr_clk_clean_buf = Signal()
|
|
self.specials += Instance("IBUFDS_GTE2",
|
|
i_CEB=disable_cdr_clk_ibuf,
|
|
i_I=cdr_clk_clean.p, i_IB=cdr_clk_clean.n,
|
|
o_O=cdr_clk_clean_buf)
|
|
qpll_drtio_settings = QPLLSettings(
|
|
refclksel=0b001,
|
|
fbdiv=4,
|
|
fbdiv_45=5,
|
|
refclk_div=1)
|
|
qpll = QPLL(cdr_clk_clean_buf, qpll_drtio_settings)
|
|
self.submodules += qpll
|
|
|
|
drtio_data_pads = []
|
|
if enable_sata:
|
|
drtio_data_pads.append(platform.request("sata"))
|
|
drtio_data_pads += [platform.request("sfp", i) for i in range(3)]
|
|
if self.platform.hw_rev == "v2.0":
|
|
drtio_data_pads.append(platform.request("sfp", 3))
|
|
|
|
if self.platform.hw_rev in ("v1.0", "v1.1"):
|
|
sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)]
|
|
self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
|
|
self.submodules.drtio_transceiver = gtp_7series.GTP(
|
|
qpll_channel=qpll.channels[0],
|
|
data_pads=drtio_data_pads,
|
|
sys_clk_freq=self.clk_freq,
|
|
rtio_clk_freq=rtio_clk_freq)
|
|
self.csr_devices.append("drtio_transceiver")
|
|
self.sync += disable_cdr_clk_ibuf.eq(
|
|
~self.drtio_transceiver.stable_clkin.storage)
|
|
|
|
if enable_sata:
|
|
sfp_channels = self.drtio_transceiver.channels[1:]
|
|
else:
|
|
sfp_channels = self.drtio_transceiver.channels
|
|
if self.platform.hw_rev in ("v1.0", "v1.1"):
|
|
self.comb += [sfp_ctl.led.eq(channel.rx_ready)
|
|
for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)]
|
|
if self.platform.hw_rev == "v2.0":
|
|
self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
|
|
for i, channel in enumerate(sfp_channels)]
|
|
|
|
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
|
|
|
|
drtioaux_csr_group = []
|
|
drtioaux_memory_group = []
|
|
drtiorep_csr_group = []
|
|
self.drtio_cri = []
|
|
for i in range(len(self.drtio_transceiver.channels)):
|
|
coreaux_name = "drtioaux" + str(i)
|
|
memory_name = "drtioaux" + str(i) + "_mem"
|
|
drtioaux_csr_group.append(coreaux_name)
|
|
drtioaux_memory_group.append(memory_name)
|
|
|
|
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
|
|
|
|
if i == 0:
|
|
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
|
|
core = cdr(DRTIOSatellite(
|
|
self.rtio_tsc, self.drtio_transceiver.channels[i],
|
|
self.rx_synchronizer))
|
|
self.submodules.drtiosat = core
|
|
self.csr_devices.append("drtiosat")
|
|
else:
|
|
corerep_name = "drtiorep" + str(i-1)
|
|
drtiorep_csr_group.append(corerep_name)
|
|
|
|
core = cdr(DRTIORepeater(
|
|
self.rtio_tsc, self.drtio_transceiver.channels[i]))
|
|
setattr(self.submodules, corerep_name, core)
|
|
self.drtio_cri.append(core.cri)
|
|
self.csr_devices.append(corerep_name)
|
|
|
|
coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw))
|
|
setattr(self.submodules, coreaux_name, coreaux)
|
|
self.csr_devices.append(coreaux_name)
|
|
|
|
memory_address = self.mem_map["drtioaux"] + 0x800*i
|
|
self.add_wb_slave(memory_address, 0x800,
|
|
coreaux.bus)
|
|
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
|
|
self.config["HAS_DRTIO"] = None
|
|
self.config["HAS_DRTIO_ROUTING"] = None
|
|
self.add_csr_group("drtioaux", drtioaux_csr_group)
|
|
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
|
|
self.add_csr_group("drtiorep", drtiorep_csr_group)
|
|
|
|
i2c = self.platform.request("i2c")
|
|
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
|
self.csr_devices.append("i2c")
|
|
self.config["I2C_BUS_COUNT"] = 1
|
|
|
|
rtio_clk_period = 1e9/rtio_clk_freq
|
|
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
|
|
if with_wrpll:
|
|
self.submodules.wrpll_sampler = DDMTDSamplerGTP(
|
|
self.drtio_transceiver,
|
|
platform.request("cdr_clk_clean_fabric"))
|
|
helper_clk_pads = platform.request("ddmtd_helper_clk")
|
|
self.submodules.wrpll = WRPLL(
|
|
helper_clk_pads=helper_clk_pads,
|
|
main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
|
|
helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
|
|
ddmtd_inputs=self.wrpll_sampler)
|
|
self.csr_devices.append("wrpll")
|
|
# note: do not use self.wrpll.cd_helper.clk; otherwise, vivado craps out with:
|
|
# critical warning: create_clock attempting to set clock on an unknown port/pin
|
|
# command: "create_clock -period 7.920000 -waveform {0.000000 3.960000} -name
|
|
# helper_clk [get_xlnx_outside_genome_inst_pin 20 0]
|
|
platform.add_period_constraint(helper_clk_pads.p, rtio_clk_period*0.99)
|
|
platform.add_false_path_constraints(self.crg.cd_sys.clk, helper_clk_pads.p)
|
|
else:
|
|
self.submodules.siphaser = SiPhaser7Series(
|
|
si5324_clkin=platform.request("cdr_clk") if platform.hw_rev == "v2.0"
|
|
else platform.request("si5324_clkin"),
|
|
rx_synchronizer=self.rx_synchronizer,
|
|
ref_clk=self.crg.clk125_div2, ref_div2=True,
|
|
rtio_clk_freq=rtio_clk_freq)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
|
|
self.csr_devices.append("siphaser")
|
|
self.config["HAS_SI5324"] = None
|
|
self.config["SI5324_SOFT_RESET"] = None
|
|
|
|
gtp = self.drtio_transceiver.gtps[0]
|
|
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
|
|
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk,
|
|
gtp.txoutclk, gtp.rxoutclk)
|
|
if with_wrpll:
|
|
platform.add_false_path_constraints(
|
|
helper_clk_pads.p, gtp.rxoutclk)
|
|
for gtp in self.drtio_transceiver.gtps[1:]:
|
|
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk, gtp.rxoutclk)
|
|
|
|
self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
|
|
self.csr_devices.append("rtio_crg")
|
|
fix_serdes_timing_path(platform)
|
|
|
|
def add_rtio(self, rtio_channels, sed_lanes=8):
|
|
# Only add MonInj core if there is anything to monitor
|
|
if any([len(c.probes) for c in rtio_channels]):
|
|
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
|
self.csr_devices.append("rtio_moninj")
|
|
|
|
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels, lane_count=sed_lanes)
|
|
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
|
|
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
|
[self.drtiosat.cri],
|
|
[self.local_io.cri] + self.drtio_cri,
|
|
mode="sync", enable_routing=True)
|
|
self.csr_devices.append("cri_con")
|
|
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
|
|
self.csr_devices.append("routing_table")
|
|
|
|
|
|
class Master(MasterBase):
|
|
def __init__(self, hw_rev=None, **kwargs):
|
|
if hw_rev is None:
|
|
hw_rev = "v2.0"
|
|
MasterBase.__init__(self, hw_rev=hw_rev, **kwargs)
|
|
|
|
self.rtio_channels = []
|
|
|
|
phy = ttl_simple.Output(self.platform.request("user_led", 0))
|
|
self.submodules += phy
|
|
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
# matches Tester EEM numbers
|
|
eem.DIO.add_std(self, 5,
|
|
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
|
|
eem.Urukul.add_std(self, 0, 1, ttl_serdes_7series.Output_8X)
|
|
|
|
self.config["HAS_RTIO_LOG"] = None
|
|
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
|
self.rtio_channels.append(rtio.LogChannel())
|
|
|
|
self.add_rtio(self.rtio_channels)
|
|
|
|
|
|
class Satellite(SatelliteBase):
|
|
def __init__(self, hw_rev=None, **kwargs):
|
|
if hw_rev is None:
|
|
hw_rev = "v2.0"
|
|
SatelliteBase.__init__(self, hw_rev=hw_rev, **kwargs)
|
|
|
|
self.rtio_channels = []
|
|
phy = ttl_simple.Output(self.platform.request("user_led", 0))
|
|
self.submodules += phy
|
|
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
# matches Tester EEM numbers
|
|
eem.DIO.add_std(self, 5,
|
|
ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
|
|
|
|
self.add_rtio(self.rtio_channels)
|
|
|
|
|
|
VARIANTS = {cls.__name__.lower(): cls for cls in [Tester, SUServo, Master, Satellite]}
|
|
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="ARTIQ device binary builder for Kasli systems")
|
|
builder_args(parser)
|
|
soc_kasli_args(parser)
|
|
parser.set_defaults(output_dir="artiq_kasli")
|
|
parser.add_argument("-V", "--variant", default="tester",
|
|
help="variant: {} (default: %(default)s)".format(
|
|
"/".join(sorted(VARIANTS.keys()))))
|
|
parser.add_argument("--with-wrpll", default=False, action="store_true")
|
|
parser.add_argument("--tester-dds", default=None,
|
|
help="Tester variant DDS type: ad9910/ad9912 "
|
|
"(default: ad9910)")
|
|
parser.add_argument("--gateware-identifier-str", default=None,
|
|
help="Override ROM identifier")
|
|
args = parser.parse_args()
|
|
|
|
argdict = dict()
|
|
if args.with_wrpll:
|
|
argdict["with_wrpll"] = True
|
|
argdict["gateware_identifier_str"] = args.gateware_identifier_str
|
|
argdict["dds"] = args.tester_dds
|
|
|
|
variant = args.variant.lower()
|
|
try:
|
|
cls = VARIANTS[variant]
|
|
except KeyError:
|
|
raise SystemExit("Invalid variant (-V/--variant)")
|
|
|
|
soc = cls(**soc_kasli_argdict(args), **argdict)
|
|
build_artiq_soc(soc, builder_argdict(args))
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|