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mirror of https://github.com/m-labs/artiq.git synced 2024-12-12 21:26:37 +08:00
artiq/artiq/gateware/serwb
2018-04-03 18:48:08 +02:00
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__init__.py gateware/serwb: SERWBPLL, SERWBPHY, SERWBCore and add checks in delay finding to verify the sampling window 2017-08-30 14:40:11 +02:00
core.py gateware/serwb: add scrambling, reduce cdc fifo depth 2018-01-03 17:34:03 +01:00
etherbone.py gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender 2017-11-03 12:15:14 +01:00
kusphy.py gateware/serwb: move all clocking outside of serwb, use existing sys/sys4x clocks 2018-04-03 18:48:08 +02:00
packet.py gateware/serwb: cleanup packet 2018-01-03 17:30:12 +01:00
phy.py gateware/serwb: move all clocking outside of serwb, use existing sys/sys4x clocks 2018-04-03 18:48:08 +02:00
s7phy.py gateware/serwb: move all clocking outside of serwb, use existing sys/sys4x clocks 2018-04-03 18:48:08 +02:00
scrambler.py gateware/serwb: add scrambling, reduce cdc fifo depth 2018-01-03 17:34:03 +01:00