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Robert Jordens
324660ab40
Assume that rt2wb transactions either collide and are then reported (https://github.com/m-labs/artiq/issues/308) or that they complete and the delay with which they complete does not matter. If a transaction is ack'ed with a delay because the WB core's downstream logic is busy, that may lead to a later collision with another WB transaction. |
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.. | ||
__init__.py | ||
analyzer.py | ||
comm_dummy.py | ||
comm_generic.py | ||
comm_tcp.py | ||
core.py | ||
dds.py | ||
exceptions.py | ||
rt2wb.py | ||
runtime.py | ||
spi.py | ||
ttl.py |