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Robert Jordens
324660ab40
Assume that rt2wb transactions either collide and are then reported (https://github.com/m-labs/artiq/issues/308) or that they complete and the delay with which they complete does not matter. If a transaction is ack'ed with a delay because the WB core's downstream logic is busy, that may lead to a later collision with another WB transaction.
14 lines
352 B
Python
14 lines
352 B
Python
from artiq.language.core import *
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from artiq.language.types import *
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@syscall
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def rt2wb_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
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) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall
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def rt2wb_input(channel: TInt32) -> TInt32:
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raise NotImplementedError("syscall not simulated")
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