Florent Kermarrec f003566e52 serwb: fix rx_delay_inc on ultrascale, this was the issue serwb issue... ... rx_delay_inc and rx_delay_ce were set for only one cycle, on ultrascale, these signals are translated to serwb_serdes_5x clock domain and we now set rx_delay_inc always to 1 (MultiReg), rx_delay_ce for one cycle (PulseSynchronizer)		2017-11-18 18:01:46 +01:00
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__init__.py	gateware/serwb: SERWBPLL, SERWBPHY, SERWBCore and add checks in delay finding to verify the sampling window	2017-08-30 14:40:11 +02:00
core.py	gateware/serwb/core: cleanup and increase fifo depth	2017-11-10 10:33:39 +01:00
etherbone.py	gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender	2017-11-03 12:15:14 +01:00
kusphy.py	gateware/serwb/kusphy: use AsyncResetSynchronizer on cd_serwb_serdes_5x	2017-11-18 17:57:11 +01:00
packet.py	gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender	2017-11-03 12:15:14 +01:00
phy.py	serwb: fix rx_delay_inc on ultrascale, this was the issue serwb issue...	2017-11-18 18:01:46 +01:00
s7phy.py	gateware/serwb: change serdes clock domain to serwb_serdes	2017-08-30 15:44:44 +02:00