Robert Jördens 2f1029c292 Revert "sawg: advance dds 1/2 by one sample group" ... This reverts commit 8e0a1cbdc8. c.f. #772 The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.		2017-07-04 17:55:19 +02:00
..
__init__.py	phaser: add jesd204b rtio dds	2016-10-05 16:17:50 +02:00
accu.py	sawg: fix PhasedAccu resets	2017-07-04 11:56:21 +02:00
fir.py	dsp.fir: cleanup	2017-06-29 12:18:48 +02:00
sawg.py	Revert "sawg: advance dds 1/2 by one sample group"	2017-07-04 17:55:19 +02:00
spline.py	sawg: wire up all HBF outputs, latency compensation in phys, simplify	2016-12-14 19:16:07 +01:00
tools.py	dsp/sat_add: works after previous changes	2017-06-22 18:24:22 +02:00