mirror of https://github.com/m-labs/artiq.git
48 lines
1.4 KiB
Python
48 lines
1.4 KiB
Python
from migen import *
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from misoc.interconnect import wishbone
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from artiq.gateware.rtio import rtlink
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class RT2WB(Module):
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def __init__(self, address_width, wb=None, rtio_enable_replace=False, write_only=False):
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if wb is None:
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wb = wishbone.Interface()
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self.wb = wb
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(
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len(wb.dat_w),
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address_width + 1 if not write_only else address_width,
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enable_replace=rtio_enable_replace),
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rtlink.IInterface(
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len(wb.dat_r),
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timestamped=False) if not write_only else None
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)
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# # #
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active = Signal()
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self.sync.rio += [
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If(self.rtlink.o.stb,
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active.eq(1),
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wb.adr.eq(self.rtlink.o.address[:address_width]),
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wb.we.eq(~self.rtlink.o.address[address_width] if not write_only else 1),
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wb.dat_w.eq(self.rtlink.o.data),
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wb.sel.eq(2**len(wb.sel) - 1)
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),
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If(wb.ack,
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active.eq(0)
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)
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]
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self.comb += [
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self.rtlink.o.busy.eq(active),
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wb.cyc.eq(active),
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wb.stb.eq(active),
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]
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if not write_only:
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self.comb += [
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self.rtlink.i.stb.eq(wb.ack & ~wb.we),
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self.rtlink.i.data.eq(wb.dat_r)
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]
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