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Author SHA1 Message Date
whitequark c78aa86e72 compiler: remove dead code. 2017-04-22 15:31:32 +08:00
whitequark 032f28863f compiler: reject reachable implicit return if not returning TNone.
Fixes #718.
2017-04-22 15:31:22 +08:00
whitequark c33f9637c1 compiler: in codegen for delay(), round fp instead of truncating.
Consider delay(8*us). It results in the following computation...
  >>> 8*1e-06/1e-09
  7999.999999999999
with the result promptly getting truncated to 7999.

Fixes #706.
2017-04-22 15:31:13 +08:00
whitequark 6342829e68 conda: use GIT_FULL_HASH rather than GIT_DESCRIBE_HASH. 2017-04-22 15:30:29 +08:00
whitequark 5f53a13fec Commit missing parts of 0d0ddf2e. 2017-04-22 15:30:04 +08:00
whitequark 419042b5d3 conda: limit git hashes in build numbers to 8 chars exactly.
Before this commit, a nasty edge case was possible where repositories
on different builders have had different sets of objects fetched
into them, and so git-describe selected different lengths for
abbreviating hashes.

See also https://github.com/conda/conda-build/issues/1940.
2017-04-22 15:29:41 +08:00
Sebastien Bourdeauducq 1572d852aa conda: use conda-forge and depend on pyqtgraph 0.10.0 (#704) 2017-04-13 00:58:04 +08:00
whitequark be2683e097 compiler: fix monomorphization of coerced integer literals.
Fixes #703.
2017-04-12 13:18:24 +08:00
whitequark 90e2e22765 artiq_compile: make print() write to core log, not an invalid op.
Fixes #710.
2017-04-12 00:35:01 +08:00
Sebastien Bourdeauducq 49baba26e3 rtio: fix indentation 2017-04-06 12:41:08 +08:00
Sebastien Bourdeauducq 0a6dd963cb rtio: add a missing case for collision reporting 2017-04-06 12:41:02 +08:00
Sébastien Bourdeauducq 62068da232 scan: fix RandomScan seeding 2017-03-31 17:29:37 +08:00
Chris Ballance e8c5cb55cb language: fix PYONValue list defaults (fixes #682) 2017-03-29 21:59:48 +08:00
Chris Ballance 483a897db4 monkey_patches: fix 3af29f7 2017-03-29 09:24:41 +08:00
Sebastien Bourdeauducq bf86828445 add missing artiq-dev.yaml 2017-03-03 18:07:03 +08:00
Sebastien Bourdeauducq 55f217ceef conda: use artiq-dev system 2017-03-03 18:02:46 +08:00
whitequark 37c9b97bc4 compiler.types: add missing TTuple.__hash__ implementation. 2017-03-03 17:40:15 +08:00
whitequark 90aeb76a2c transforms.inferencer: do not unnecessarily mutate typedtree.
This caused the hash to change after every iteration of inference,
if the result of any coercion was an integer of indefinite width.
2017-03-03 11:02:16 +08:00
whitequark 007ae00459 compiler.embedding: fix an overly lax hasher. 2017-03-03 11:02:16 +08:00
whitequark fd5cdb7d1e compiler.transforms: implement a typedtree printer. 2017-03-03 11:02:16 +08:00
Robert Jördens 791976e6d0 conda: pyqt >= 5.5 2017-03-02 23:14:58 +01:00
Chris Ballance 3ae7fde21f conda: use anaconda default pyqt (fixes #670) 2017-03-02 23:14:58 +01:00
whitequark d4673d5b17 compiler.embedding: use attribute count in fixpoint condition.
Before this commit, we had a hack where inferencing would run
one more time, in case we can still infer more attributes even
after all the type information is there. This doesn't work
if *that* round of inferencing brings even more code, e.g.
this is easy to trigger with context managers.
2017-03-01 11:51:25 +08:00
Robert Jördens 72bf39f593 monkey_patches: cleanup 2017-02-28 21:42:25 +08:00
Chris Ballance 349774e65e monkey-patch Python 3.5.3 asyncio.base_events._ipaddr_info
this fixes #506 for py3.5.3
2017-02-28 21:42:21 +08:00
Sebastien Bourdeauducq c777ae8ae9 protocols: increase asyncio line limit. Closes #671 2017-02-17 20:46:38 +08:00
Sebastien Bourdeauducq f5cd0928c3 RELEASE_NOTES: 2.2 2017-02-01 09:38:26 +08:00
Robert Jördens abb5b8aba5 artiq_flash: fix scripts_path 2017-02-01 09:04:57 +08:00
Robert Jördens e3260beb0c RELEASING: use signed annotated tags 2017-02-01 08:28:19 +08:00
Sebastien Bourdeauducq 6e641427f0 RELEASING: mention GitHub releases 2017-02-01 08:28:09 +08:00
Sebastien Bourdeauducq e6a8d96b7c RELEASING: mention doc redirect 2017-02-01 08:28:09 +08:00
whitequark 31dd99e8bd compiler: the len builtin is not polymorphic, coerce the result.
Fixes #659.
2017-02-01 08:23:30 +08:00
whitequark 7516e6d800 Fix 2f37b1d. 2017-02-01 08:23:24 +08:00
whitequark 2dc8d417ca compiler: support methods defined on singleton instances.
Fixes #638.
2017-02-01 08:23:16 +08:00
Robert Jördens 1845a134e5 Relicense ARTIQ as LGPLv3+ (closes #570)
Kelly Stevens: 1481043941095.63542@gtri.gatech.edu
David Nadlinger: E7C03799-5D45-4C03-9DF9-029FE2B4F12B@klickverbot.at
whitequark: 69d1ca29d5ab03fbcfb446d65cbe1150@mail.whitequark.org
Felix Held: 9145cc19-2319-3516-b2a9-dde60aef11f7@felixheld.de
Robert Jordens: CANb+zoFgXVYgCji_vXPauK-fnnYKpm_QioMnvmh=hvLFWQONWA@mail.gmail.com
Daniel Slichter: BL2PR09MB1010FE3D3A325E889AD70A2591820@BL2PR09MB1010.namprd09.prod.outlook.com
Joe Britton: CAE2_b1V60_6PJ3VYx_s-p5XVfKJUx8kbQA7VwD3MdcmHdzROGw@mail.gmail.com
Florent Kermarrec: CA+96J6JHM8yZM=RYaporU36NdyOTL3BeSuO9oM8TTtdnXiJ5jw@mail.gmail.com
Zach Smith: CAAJ=EH+OzDs_rBJ_zTjbOZmumEZWONX2MSFUasJwf8josJGdkw@mail.gmail.com
David Leibrandt: CY1PR09MB0921C628EC76CDFC4CC7F64F95820@CY1PR09MB0921.namprd09.prod.outlook.com
Raghavendra Srinivas: DM5PR09MB1531C49EEE1774DF2BA80616F8850@DM5PR09MB1531.namprd09.prod.outlook.com
Yann Sionneau: CACi+aWbdY48D9CgKtXdtVsdX4NS1JwVN4v-PCC17F_rPKSt4XQ@mail.gmail.com
Sébastien Bourdeauducq: c3f235dc-e9c5-7f7a-10f2-bb4e4f85e7f5@m-labs.hk
2017-01-27 11:20:57 +01:00
Robert Jördens a69f45f7c8 doc: use napoleon (for pdq2) 2017-01-26 18:21:47 +01:00
Robert Jördens d16f5ce540 artiq_flash: make scripts_path a function (for doc generating) 2017-01-26 18:21:43 +01:00
Robert Jördens b4df00009b doc/conda: fix conda env description syntax 2017-01-26 18:20:30 +01:00
Robert Jördens 25ff94dbfa doc: use minimal conda environment to build 2017-01-26 18:20:30 +01:00
Robert Jördens 4a35428518 doc: fix autodoc search path 2017-01-26 18:20:30 +01:00
Robert Jördens 13912b66f3 doc: minimize dependencies for manual 2017-01-26 18:20:30 +01:00
Robert Jördens 6c995e1f07 conda: fix sphinx pin 2017-01-26 00:54:00 +01:00
Robert Jördens 364bd726bb conda: pin sphinx to 1.4.8 (closes #645)
can be reverted when https://github.com/snide/sphinx_rtd_theme/pull/346 is
released
2017-01-26 00:51:50 +01:00
Sebastien Bourdeauducq 4d5ba3fb03 doc: fix table formatting problem, add 'string constant' as supported compiler type 2017-01-16 13:58:27 -06:00
Sebastien Bourdeauducq ec130f967d update copyright year 2017-01-04 11:35:37 +01:00
Robert Jördens 660b067708 spi: fix xfers with full data_width (closes #615)
misoc 15000af43611bbe8be13cb2b016e408f043202cd
2017-01-03 19:50:15 +01:00
Sebastien Bourdeauducq 453b29ad78 RELEASE_NOTES: 2.1 2016-12-12 13:00:07 +08:00
Sebastien Bourdeauducq 2962c95148 set asyncio loop earlier in controllers (#627) 2016-12-12 11:38:52 +08:00
Sebastien Bourdeauducq b823e916f0 Revert "pc_rpc: use ProactorEventLoop on Windows (#627)"
This reverts commit 7d4297b9bb.
2016-12-12 11:38:52 +08:00
Sebastien Bourdeauducq 072e7f6628 pc_rpc: use ProactorEventLoop on Windows (#627) 2016-11-24 10:18:27 +08:00
whitequark ebae6d248f compiler: unbreak casts to int32/int64. 2016-11-21 14:22:35 +00:00
whitequark ebb3205dff analyses.constness: fix false positive on x[...]. 2016-11-21 14:22:34 +00:00
whitequark fd1d77767e inferencer: significantly improve the op-assignment diagnostic.
Before this commit, it displayed incorrect output if an error
appeared on 2nd run and beyond, and displayed messages for trying
to do "num32 -= num64" that made very little sense.
2016-11-21 14:22:32 +00:00
whitequark 372e8f9b2b llvm_ir_generator: handle no-op coercions. 2016-11-21 10:58:42 +08:00
Sebastien Bourdeauducq 0da2202179 moninj: add min declaration 2016-11-21 00:06:35 +08:00
whitequark ec645d3589 coredevice.dds: work around the round(numpy.float64()) snafu. 2016-11-20 21:54:21 +08:00
whitequark 5119fa394d coredevice.dds: update from obsolete int(width=) syntax (fixes #621). 2016-11-20 21:54:20 +08:00
David Leibrandt 99104499f9 gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 2016-11-20 15:22:08 +08:00
Sebastien Bourdeauducq 2513511775 gui: 2.0 -> 2 in logo 2016-11-20 15:14:43 +08:00
whitequark b85ab712a9 artiq_compile: actually disable attribute writeback.
I wrote both halves of this condition but forgot to hook
them together.

Fixes #586.
2016-11-10 01:04:48 +00:00
David Nadlinger f368e1b228 compiler: Clarify recv_rpc value names and documentation [nfc]
Previously, the phi emitted for the pointer parameter to recv_rpc was –
rather confusingly – called "size", and the pseudo-code in the comment
had bit-rotted.

Signed-off-by: David Nadlinger <code@klickverbot.at>
2016-11-07 22:47:18 +08:00
David Nadlinger 4c2e921270 compiler: Fix break/continue targets in loop else blocks
Previously, they would still target the respective labels in the
just-exited loop.

Signed-off-by: David Nadlinger <code@klickverbot.at>
2016-11-05 17:27:36 +08:00
David Nadlinger d5974b3af5 runtime/moninj: Don't try to pack more than 64 channels
Since the status words are only 8 bytes wide, left-shifting
by more than that is undefined behaviour (although it seems like
we got lucky and Clang dind't decide to optimise the whole
implementation away).

See GitHub #601.

Signed-off-by: David Nadlinger <code@klickverbot.at>
2016-11-05 00:29:11 +08:00
David Nadlinger 4e03f7ab0a gui: Don't show more than the 64 working channels in moninj
Previously, you could irreversibly set the override since
the gateware part would accept commands for the higher channels,
but of coure not report back the results.

See GitHub #601.

Signed-off-by: David Nadlinger <code@klickverbot.at>
2016-11-05 00:29:11 +08:00
Sebastien Bourdeauducq 29e3333467 manual: Vivado is now default 2016-11-04 11:54:56 +08:00
Sebastien Bourdeauducq 67ce341adf master: keep dataset manager consistent when set_dataset is called with contradictory attributes 2016-10-18 17:11:29 +08:00
Sebastien Bourdeauducq 363a7ebe3a master: ensure same dataset is in broadcast and local when mutating 2016-10-18 17:11:29 +08:00
Sebastien Bourdeauducq 5ecfa8197f doc: clarify usage of pause/check_pause, closes #571 2016-10-17 20:08:43 +08:00
Sebastien Bourdeauducq 115204f2f4 dashboard/datasets: use scientific spinbox and increase number of decimals, closes #572 2016-10-17 20:08:39 +08:00
Sebastien Bourdeauducq 00402c9af9 conda: update migen version requirements 2016-09-24 21:02:32 +08:00
Robert Jördens a9bef3c7d0 RELEASE_NOTES: 2.0 2016-09-24 00:41:39 +02:00
Sebastien Bourdeauducq 03c26f9c96 novatech409b: fix get_status 2016-09-23 11:03:37 +08:00
Sebastien Bourdeauducq 638bbeca48 dashboard: make state restore failure on experiment opening non-fatal 2016-09-21 19:23:31 +08:00
Robert Jördens 122d48d2d5 pipistrello: shrink a few more fifos 2016-09-21 02:45:52 +02:00
Robert Jördens 6d715d0d4d README: GPLv3+ 2016-09-15 09:51:47 -04:00
Robert Jördens 6073aa7590 RELEASE_NOTES: 2.0rc2 2016-09-14 21:53:36 -04:00
whitequark 6f2125258c compiler: skip kernel_invariant linting for exception types. 2016-09-14 21:49:43 -04:00
whitequark ecb01d055f compiler: warn about unused kernel_invariant entries.
Fixes #543.
2016-09-14 21:49:43 -04:00
whitequark fb3585f5b0 coreanalyzer: fix rtio_log message extraction.
Fixes #550.
2016-09-14 18:36:55 +08:00
Sebastien Bourdeauducq 898fa43ecc dashboard: remember experiment editor scroll positions 2016-09-14 10:52:49 +08:00
Sebastien Bourdeauducq 9de0dacb94 dashboard: save/restore MDI window states when they are closed. Closes #559 2016-09-14 10:45:00 +08:00
Sebastien Bourdeauducq f644595489 gui: use bare QSpinBox for integer NumberEntries. Closes #558 2016-09-14 10:29:29 +08:00
Sebastien Bourdeauducq 736927b6da language: set NoScan default repetitions to 1 2016-09-13 11:49:21 +08:00
raghu d4af4414e7 added repetitions for no scan, repetitions set to one when disable other scans selected. Closes #532 2016-09-13 11:49:21 +08:00
whitequark b73d7e402c runtime: expose strlen (implicitly required for comparing strings).
Fixes #557.
2016-09-10 09:53:21 +08:00
Sebastien Bourdeauducq ad697d4320 master: optimize repository scan, closes #546 2016-09-10 00:19:53 +08:00
Sebastien Bourdeauducq f23ebc035b doc: move VADJ, closes #554 2016-09-09 18:41:36 +08:00
whitequark e75002a109 Also serialize numpy.int{32,64} like int in RPC return values.
Fixes #555.
2016-09-09 17:17:51 +08:00
Sebastien Bourdeauducq f2502026bf gui/applets: fix teardown of half-initialized applets 2016-09-06 23:07:29 +08:00
Sebastien Bourdeauducq 9e33bceb6f gui/applets: fix handling of process creation failure 2016-09-06 23:07:22 +08:00
Sebastien Bourdeauducq 76c407b4b9 dashboard: fix 'disable other scans' 2016-09-06 22:50:35 +08:00
Sebastien Bourdeauducq d571c52800 artiq_client: fix 'show log', closes #552 2016-09-05 23:05:58 +08:00
Robert Jördens 87fad87e8f RELEASE_NOTES: 2.0rc1 2016-09-04 16:33:33 +02:00
Robert Jördens 642c7abdad conda: fix nist_clock summary 2016-09-03 11:08:58 +02:00
Sebastien Bourdeauducq c9eeddbb9f import_cache: make sure last line ends with \n as linecache does. Closes #547 2016-09-02 11:02:40 +08:00
Sebastien Bourdeauducq bb12f563f6 gui: fix layout and scan disable bugs with argument recomputation 2016-09-02 11:02:35 +08:00
Sebastien Bourdeauducq e0cdda2760 dashboard: fix argument recomputation for experiments outside repository. Closes #548 2016-09-02 11:02:29 +08:00
Sebastien Bourdeauducq 584d88428f RELEASE_NOTES: None arguments during experiment examination (#545) 2016-09-02 11:02:25 +08:00
Robert Jördens fc4b3e44d5 spi: use misoc SPIMachine, closes #314 2016-08-26 14:09:05 +02:00
Robert Jördens 9d08011a1f conda: misoc 0.3 2016-08-26 14:09:05 +02:00
Robert Jördens 75731611cd doc/manual: no analytics_id with rtd 2016-08-25 22:21:40 +02:00
Robert Jördens c4559fcd99 doc: use sphinx_rtd_theme 2016-08-25 21:53:50 +02:00
Robert Jördens afd2a37e0d doc/rtio: cleanup 2016-08-25 21:53:50 +02:00
Robert Jördens 8f045911f1 doc/rtio: make vis coloring consistent 2016-08-25 19:28:36 +02:00
Robert Jördens 6b5424b118 doc/rtio: vis RTIOUndeflow tweak 2016-08-25 19:28:36 +02:00
Robert Jördens e0569a1531 doc/rtio: vis RTIOUnderflow 2016-08-25 19:28:36 +02:00
Robert Jördens 6e8ff374d7 doc/rtio: input vis 2016-08-25 19:28:36 +02:00
Robert Jördens aef99b5164 doc/rtio: vis: now_mu -> now since not didactically relevant 2016-08-25 19:28:36 +02:00
Robert Jördens 1c9005851e doc/rtio: handover vis, tweak other vis's 2016-08-25 19:28:36 +02:00
Robert Jördens 87d3b53bde doc/rtio: sync() visualization 2016-08-25 19:28:36 +02:00
Robert Jördens 19d6dbc8a9 doc: ship wavedrom js b/c https 2016-08-25 19:28:36 +02:00
Robert Jördens 1f31fa620a doc: use wavedrom to visualize stuff 2016-08-25 12:16:05 +02:00
Robert Jördens c8faff2ba7 doc/rtio: fix description of idle kernel/reset 2016-08-25 10:20:10 +02:00
Robert Jördens 2da1dbae91 doc: rtio concepts, closes #451 2016-08-24 17:50:39 +02:00
Robert Jördens 1c85e95ad0 doc: expand/refine getting_started_core 2016-08-24 17:50:39 +02:00
Robert Jördens e07fd019aa doc: cleanup git checkout instructions (see #542) 2016-08-24 17:50:39 +02:00
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Library.

View File

@ -30,4 +30,17 @@ Website: https://m-labs.hk/artiq
`Cite ARTIQ <http://dx.doi.org/10.5281/zenodo.51303>`_ as ``Bourdeauducq, Sébastien et al. (2016). ARTIQ 1.0. Zenodo. 10.5281/zenodo.51303``.
Copyright (C) 2014-2016 M-Labs Limited. Licensed under GNU GPL version 3.
Copyright (C) 2014-2017 M-Labs Limited.
ARTIQ is free software: you can redistribute it and/or modify
it under the terms of the GNU Lesser General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ARTIQ is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public License
along with ARTIQ. If not, see <http://www.gnu.org/licenses/>.

View File

@ -3,8 +3,38 @@
Release notes
=============
unreleased [2.x]
----------------
2.3
---
* When using conda, add the conda-forge channel before installing ARTIQ.
2.2
---
No further notes.
2.1
---
No further notes.
2.0
---
No further notes.
2.0rc2
------
No further notes.
2.0rc1
------
* The format of the influxdb pattern file is simplified. The procedure to
edit patterns is also changed to modifying the pattern file and calling:
@ -34,6 +64,8 @@ unreleased [2.x]
(i.e. grouping by day and then by hour, instead of by day and then by minute)
* The ``parent`` keyword argument of ``HasEnvironment`` (and ``EnvExperiment``)
has been replaced. Pass the parent as first argument instead.
* During experiment examination (and a fortiori repository scan), the values of
all arguments are set to ``None`` regardless of any default values supplied.
* In the dashboard's experiment windows, partial or full argument recomputation
takes into account the repository revision field.
* By default, ``NumberValue`` and ``Scannable`` infer the scale from the unit
@ -50,6 +82,7 @@ unreleased [2.x]
numpy.int64). If you pass an integer as a RPC argument, the target function
receives a numpy type.
1.3
---

View File

@ -11,9 +11,11 @@ Major releases
3. Ensure that release versions of all packages required are available under the ``main`` label in conda. Ensure that new packages in ``main`` do not break older ARTIQ releases.
4. In the release-X branch, remove any unfinished features.
5. Test and fix any problems found. Apply fixes to both master and release-X.
6. If you have willing testers for release candidates, tag X.0rc1 in the release-X branch, have it build, and point testers there. Iterate over the previous points with new release candidates if necessary.
6. If you have willing testers for release candidates, tag X.0rc1 in the release-X branch (generally use signed annotated tags, i.e. ``git tag -sa X.0rc1``), have it build, and point testers there. Iterate over the previous points with new release candidates if necessary.
7. Tag X.0 in the release-X branch, build it, and copy its packages to ``main`` channel.
8. Mint a new DOI from Zenodo and update the README/introduction.
9. Update the m-labs.hk/artiq/manual redirect to point to m-labs.hk/artiq/manual-release-X (edit /artiq/.htaccess).
10. "Draft a new release" on GitHub.
Minor (bugfix) releases
-----------------------
@ -21,3 +23,4 @@ Minor (bugfix) releases
1. Backport bugfixes from the master branch or fix bugs specific to old releases into the currently maintained release-X branch(es).
2. When significant bugs have been fixed, tag X.Y+1.
3. To help dealing with regressions, no new features or refactorings should be implemented in release-X branches. Those happen in the master branch, and then a new release-X+1 branch is created.
4. "Draft a new release" on GitHub.

View File

@ -9,7 +9,7 @@ import h5py
from artiq import __artiq_dir__ as artiq_dir
from artiq.gui.tools import LayoutWidget, log_level_to_name, get_open_file_name
from artiq.gui.entries import argty_to_entry
from artiq.gui.entries import procdesc_to_entry
from artiq.protocols import pyon
from artiq.master.worker import Worker, log_worker_exception
@ -48,7 +48,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
self.viewport().installEventFilter(_WheelFilter(self.viewport()))
self._groups = dict()
self._arg_to_entry_widgetitem = dict()
self._arg_to_widgets = dict()
self._dock = dock
if not self._dock.arguments:
@ -59,12 +59,13 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
gradient.setColorAt(1, self.palette().midlight().color())
for name, argument in self._dock.arguments.items():
try:
entry = argty_to_entry[argument["desc"]["ty"]](argument)
except:
print(name, argument)
widgets = dict()
self._arg_to_widgets[name] = widgets
entry = procdesc_to_entry(argument["desc"])(argument)
widget_item = QtWidgets.QTreeWidgetItem([name])
self._arg_to_entry_widgetitem[name] = entry, widget_item
widgets["entry"] = entry
widgets["widget_item"] = widget_item
for col in range(3):
widget_item.setBackground(col, gradient)
@ -77,6 +78,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
else:
self._get_group(argument["group"]).addChild(widget_item)
fix_layout = LayoutWidget()
widgets["fix_layout"] = fix_layout
fix_layout.addWidget(entry)
self.setItemWidget(widget_item, 1, fix_layout)
@ -146,16 +148,18 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
argument = self._dock.arguments[name]
procdesc = arginfo[name][0]
state = argty_to_entry[procdesc["ty"]].default_state(procdesc)
state = procdesc_to_entry(procdesc).default_state(procdesc)
argument["desc"] = procdesc
argument["state"] = state
old_entry, widget_item = self._arg_to_entry_widgetitem[name]
old_entry.deleteLater()
widgets = self._arg_to_widgets[name]
entry = argty_to_entry[procdesc["ty"]](argument)
self._arg_to_entry_widgetitem[name] = entry, widget_item
self.setItemWidget(widget_item, 1, entry)
widgets["entry"].deleteLater()
widgets["entry"] = procdesc_to_entry(procdesc)(argument)
widgets["fix_layout"] = LayoutWidget()
widgets["fix_layout"].addWidget(widgets["entry"])
self.setItemWidget(widgets["widget_item"], 1, widgets["fix_layout"])
self.updateGeometries()
def save_state(self):
expanded = []
@ -314,7 +318,7 @@ class _ExperimentDock(QtWidgets.QMdiSubWindow):
"class_name": class_name,
"log_level": self.options["log_level"],
"arguments": {
name: argty_to_entry[argument["desc"]["ty"]].state_to_value(
name: procdesc_to_entry(argument["desc"]).state_to_value(
argument["state"])
for name, argument in self.arguments.items()},
}
@ -466,7 +470,7 @@ class ExperimentsArea(QtWidgets.QMdiArea):
def initialize_submission_arguments(self, arginfo):
arguments = OrderedDict()
for name, (procdesc, group) in arginfo.items():
state = argty_to_entry[procdesc["ty"]].default_state(procdesc)
state = procdesc_to_entry(procdesc).default_state(procdesc)
arguments[name] = {
"desc": procdesc,
"group": group,

View File

@ -17,6 +17,12 @@ class Constness(algorithm.Visitor):
self.visit(node.targets)
self.in_assign = False
def visit_SubscriptT(self, node):
old_in_assign, self.in_assign = self.in_assign, False
self.visit(node.value)
self.visit(node.slice)
self.in_assign = old_in_assign
def visit_AttributeT(self, node):
self.generic_visit(node)
if self.in_assign:

View File

@ -126,10 +126,10 @@ def fn_int():
return types.TConstructor(TInt())
def fn_int32():
return types.TConstructor(TInt32())
return types.TBuiltinFunction("int32")
def fn_int64():
return types.TConstructor(TInt64())
return types.TBuiltinFunction("int64")
def fn_float():
return types.TConstructor(TFloat())

View File

@ -15,7 +15,7 @@ from Levenshtein import ratio as similarity, jaro_winkler
from ..language import core as language_core
from . import types, builtins, asttyped, prelude
from .transforms import ASTTypedRewriter, Inferencer, IntMonomorphizer
from .transforms import ASTTypedRewriter, Inferencer, IntMonomorphizer, TypedtreePrinter
from .transforms.asttyped_rewriter import LocalExtractor
@ -85,6 +85,14 @@ class EmbeddingMap:
n += 1
new_instance_type.name = "{}.{}".format(new_instance_type.name, n)
def attribute_count(self):
count = 0
for host_type in self.type_map:
instance_type, constructor_type = self.type_map[host_type]
count += len(instance_type.attributes)
count += len(constructor_type.attributes)
return count
# Functions
def store_function(self, function, ir_function_name):
self.function_map[function] = ir_function_name
@ -382,23 +390,6 @@ class ASTSynthesizer:
return node
def assign_attribute(self, obj, attr_name, value):
obj_node = self.quote(obj)
dot_loc = self._add(".")
name_loc = self._add(attr_name)
_ = self._add(" ")
equals_loc = self._add("=")
_ = self._add(" ")
value_node = self.quote(value)
attr_node = asttyped.AttributeT(value=obj_node, attr=attr_name, ctx=None,
type=value_node.type,
dot_loc=dot_loc, attr_loc=name_loc,
loc=obj_node.loc.join(name_loc))
return ast.Assign(targets=[attr_node], value=value_node,
op_locs=[equals_loc], loc=name_loc.join(value_node.loc))
def suggest_identifier(id, names):
sorted_names = sorted(names, key=lambda other: jaro_winkler(id, other), reverse=True)
@ -561,7 +552,13 @@ class StitchingInferencer(Inferencer):
# of having the host-to-ARTIQ mapping code in only one place and
# also immediately getting proper diagnostics on type errors.
attr_value = getattr(object_value, attr_name)
if inspect.ismethod(attr_value) and types.is_instance(object_type):
if (inspect.ismethod(attr_value) and
types.is_instance(object_type) and
# Check that the method is indeed defined on the class,
# and not just this instance. The check is written in
# the inverted form and not as hasattr(type(attr_value))
# since the method may as well be defined on a superclass.
attr_name not in object_value.__dict__):
# In cases like:
# class c:
# @kernel
@ -671,6 +668,8 @@ class TypedtreeHasher(algorithm.Visitor):
def freeze(obj):
if isinstance(obj, ast.AST):
return self.visit(obj)
elif isinstance(obj, list):
return hash(tuple(freeze(elem) for elem in obj))
elif isinstance(obj, types.Type):
return hash(obj.find())
else:
@ -683,7 +682,7 @@ class TypedtreeHasher(algorithm.Visitor):
return hash(tuple(freeze(getattr(node, field_name)) for field_name in fields))
class Stitcher:
def __init__(self, core, dmgr, engine=None):
def __init__(self, core, dmgr, engine=None, print_as_rpc=True):
self.core = core
self.dmgr = dmgr
if engine is None:
@ -699,7 +698,8 @@ class Stitcher:
# We don't want some things from the prelude as they are provided in
# the host Python namespace and gain special meaning when quoted.
self.prelude = prelude.globals()
self.prelude.pop("print")
if print_as_rpc:
self.prelude.pop("print")
self.prelude.pop("array")
self.functions = {}
@ -719,22 +719,48 @@ class Stitcher:
inferencer = StitchingInferencer(engine=self.engine,
value_map=self.value_map,
quote=self._quote)
hasher = TypedtreeHasher()
typedtree_hasher = TypedtreeHasher()
# Iterate inference to fixed point.
old_typedtree_hash = None
old_attr_count = None
while True:
inferencer.visit(self.typedtree)
typedtree_hash = hasher.visit(self.typedtree)
typedtree_hash = typedtree_hasher.visit(self.typedtree)
attr_count = self.embedding_map.attribute_count()
if old_typedtree_hash == typedtree_hash:
if old_typedtree_hash == typedtree_hash and old_attr_count == attr_count:
break
old_typedtree_hash = typedtree_hash
old_attr_count = attr_count
# When we have an excess of type information, sometimes we can infer every type
# in the AST without discovering every referenced attribute of host objects, so
# do one last pass unconditionally.
inferencer.visit(self.typedtree)
# After we've discovered every referenced attribute, check if any kernel_invariant
# specifications refers to ones we didn't encounter.
for host_type in self.embedding_map.type_map:
instance_type, constructor_type = self.embedding_map.type_map[host_type]
if not hasattr(instance_type, "constant_attributes"):
# Exceptions lack user-definable attributes.
continue
for attribute in instance_type.constant_attributes:
if attribute in instance_type.attributes:
# Fast path; if the ARTIQ Python type has the attribute, then every observed
# value is guaranteed to have it too.
continue
for value, loc in self.value_map[instance_type]:
if hasattr(value, attribute):
continue
diag = diagnostic.Diagnostic("warning",
"object {value} of type {typ} declares attribute '{attr}' as "
"kernel invariant, but the instance referenced here does not "
"have this attribute",
{"value": repr(value),
"typ": types.TypePrinter().name(instance_type, max_depth=0),
"attr": attribute},
loc)
self.engine.process(diag)
# After we have found all functions, synthesize a module to hold them.
source_buffer = source.Buffer("", "<synthesized>")

View File

@ -29,7 +29,10 @@ def hook_exec_module(self, module):
fn = module.__file__
try:
with tokenize.open(fn) as fp:
cache[fn] = fp.readlines()
lines = fp.readlines()
if lines and not lines[-1].endswith("\n"):
lines[-1] += "\n"
cache[fn] = lines
except:
logger.warning("failed to add '%s' to cache", fn, exc_info=True)
else:

View File

@ -40,7 +40,8 @@ class Source:
return cls(source.Buffer(f.read(), filename, 1), engine=engine)
class Module:
def __init__(self, src, ref_period=1e-6):
def __init__(self, src, ref_period=1e-6, attribute_writeback=True):
self.attribute_writeback = attribute_writeback
self.engine = src.engine
self.embedding_map = src.embedding_map
self.name = src.name
@ -79,7 +80,8 @@ class Module:
llvm_ir_generator = transforms.LLVMIRGenerator(
engine=self.engine, module_name=self.name, target=target,
embedding_map=self.embedding_map)
return llvm_ir_generator.process(self.artiq_ir, attribute_writeback=True)
return llvm_ir_generator.process(self.artiq_ir,
attribute_writeback=self.attribute_writeback)
def entry_point(self):
"""Return the name of the function that is the entry point of this module."""

View File

@ -14,6 +14,8 @@ def globals():
"list": builtins.fn_list(),
"array": builtins.fn_array(),
"range": builtins.fn_range(),
"int32": builtins.fn_int32(),
"int64": builtins.fn_int64(),
# Exception constructors
"Exception": builtins.fn_Exception(),

View File

@ -6,3 +6,4 @@ from .artiq_ir_generator import ARTIQIRGenerator
from .dead_code_eliminator import DeadCodeEliminator
from .llvm_ir_generator import LLVMIRGenerator
from .interleaver import Interleaver
from .typedtree_printer import TypedtreePrinter

View File

@ -317,7 +317,15 @@ class ARTIQIRGenerator(algorithm.Visitor):
self.current_block.append(ir.Return(ir.Constant(None, builtins.TNone())))
else:
if not self.current_block.is_terminated():
if len(self.current_block.predecessors()) != 0:
diag = diagnostic.Diagnostic("error",
"this function must return a value of type {typ} explicitly",
{"typ": types.TypePrinter().name(typ.ret)},
node.keyword_loc)
self.engine.process(diag)
self.current_block.append(ir.Unreachable())
finally:
self.name = old_name
self.current_args = old_args
@ -452,38 +460,39 @@ class ARTIQIRGenerator(algorithm.Visitor):
self.current_block = body
self.visit(node.body)
post_body = self.current_block
if any(node.orelse):
else_tail = self.add_block("while.else")
self.current_block = else_tail
self.visit(node.orelse)
post_else_tail = self.current_block
tail = self.add_block("while.tail")
self.current_block = tail
if any(node.orelse):
if not post_else_tail.is_terminated():
post_else_tail.append(ir.Branch(tail))
else:
else_tail = tail
post_head.append(ir.BranchIf(cond, body, else_tail))
if not post_body.is_terminated():
post_body.append(ir.Branch(head))
break_block.append(ir.Branch(tail))
finally:
self.break_target = old_break
self.continue_target = old_continue
if any(node.orelse):
else_tail = self.add_block("while.else")
self.current_block = else_tail
self.visit(node.orelse)
post_else_tail = self.current_block
tail = self.add_block("while.tail")
self.current_block = tail
if any(node.orelse):
if not post_else_tail.is_terminated():
post_else_tail.append(ir.Branch(tail))
else:
else_tail = tail
post_head.append(ir.BranchIf(cond, body, else_tail))
if not post_body.is_terminated():
post_body.append(ir.Branch(head))
break_block.append(ir.Branch(tail))
def iterable_len(self, value, typ=_size_type):
if builtins.is_listish(value.type):
if isinstance(value, ir.Constant):
name = None
else:
name = "{}.len".format(value.name)
return self.append(ir.Builtin("len", [value], typ,
name=name))
len = self.append(ir.Builtin("len", [value], builtins.TInt32(),
name=name))
return self.append(ir.Coerce(len, typ))
elif builtins.is_range(value.type):
start = self.append(ir.GetAttr(value, "start"))
stop = self.append(ir.GetAttr(value, "stop"))
@ -541,33 +550,33 @@ class ARTIQIRGenerator(algorithm.Visitor):
self.current_assign = None
self.visit(node.body)
post_body = self.current_block
if any(node.orelse):
else_tail = self.add_block("for.else")
self.current_block = else_tail
self.visit(node.orelse)
post_else_tail = self.current_block
tail = self.add_block("for.tail")
self.current_block = tail
if any(node.orelse):
if not post_else_tail.is_terminated():
post_else_tail.append(ir.Branch(tail))
else:
else_tail = tail
if node.trip_count is not None:
head.append(ir.Loop(node.trip_count, phi, cond, body, else_tail))
else:
head.append(ir.BranchIf(cond, body, else_tail))
if not post_body.is_terminated():
post_body.append(ir.Branch(continue_block))
break_block.append(ir.Branch(tail))
finally:
self.break_target = old_break
self.continue_target = old_continue
if any(node.orelse):
else_tail = self.add_block("for.else")
self.current_block = else_tail
self.visit(node.orelse)
post_else_tail = self.current_block
tail = self.add_block("for.tail")
self.current_block = tail
if any(node.orelse):
if not post_else_tail.is_terminated():
post_else_tail.append(ir.Branch(tail))
else:
else_tail = tail
if node.trip_count is not None:
head.append(ir.Loop(node.trip_count, phi, cond, body, else_tail))
else:
head.append(ir.BranchIf(cond, body, else_tail))
if not post_body.is_terminated():
post_body.append(ir.Branch(continue_block))
break_block.append(ir.Branch(tail))
def visit_Break(self, node):
self.append(ir.Branch(self.break_target))
@ -1599,7 +1608,8 @@ class ARTIQIRGenerator(algorithm.Visitor):
return self.coerce_to_bool(arg)
else:
assert False
elif types.is_builtin(typ, "int"):
elif types.is_builtin(typ, "int") or \
types.is_builtin(typ, "int32") or types.is_builtin(typ, "int64"):
if len(node.args) == 0 and len(node.keywords) == 0:
return ir.Constant(0, node.type)
elif len(node.args) == 1 and \
@ -1723,7 +1733,7 @@ class ARTIQIRGenerator(algorithm.Visitor):
if len(node.args) == 1 and len(node.keywords) == 0:
arg = self.visit(node.args[0])
arg_mu_float = self.append(ir.Arith(ast.Div(loc=None), arg, self.ref_period))
arg_mu = self.append(ir.Coerce(arg_mu_float, builtins.TInt64()))
arg_mu = self.append(ir.Builtin("round", [arg_mu_float], builtins.TInt64()))
return self.append(ir.Builtin("delay_mu", [arg_mu], builtins.TNone()))
else:
assert False

View File

@ -5,6 +5,7 @@
from collections import OrderedDict
from pythonparser import algorithm, diagnostic, ast
from .. import asttyped, types, builtins
from .typedtree_printer import TypedtreePrinter
class Inferencer(algorithm.Visitor):
"""
@ -293,7 +294,8 @@ class Inferencer(algorithm.Visitor):
return coerced_node
elif isinstance(coerced_node, asttyped.CoerceT):
node = coerced_node
node.type, node.other_value = typ, other_node
node.type.unify(typ)
node.other_value = other_node
else:
node = asttyped.CoerceT(type=typ, value=coerced_node, other_value=other_node,
loc=coerced_node.loc)
@ -622,14 +624,28 @@ class Inferencer(algorithm.Visitor):
self._unify(node.type, builtins.TBool(),
node.loc, None)
elif types.is_builtin(typ, "int"):
valid_forms = lambda: [
valid_form("int() -> numpy.int?"),
valid_form("int(x:'a) -> numpy.int?"),
valid_form("int(x:'a, width=?) -> numpy.int?")
]
elif types.is_builtin(typ, "int") or \
types.is_builtin(typ, "int32") or types.is_builtin(typ, "int64"):
if types.is_builtin(typ, "int"):
valid_forms = lambda: [
valid_form("int() -> numpy.int?"),
valid_form("int(x:'a) -> numpy.int? where 'a is numeric")
]
result_typ = builtins.TInt()
elif types.is_builtin(typ, "int32"):
valid_forms = lambda: [
valid_form("numpy.int32() -> numpy.int32"),
valid_form("numpy.int32(x:'a) -> numpy.int32 where 'a is numeric")
]
result_typ = builtins.TInt32()
elif types.is_builtin(typ, "int64"):
valid_forms = lambda: [
valid_form("numpy.int64() -> numpy.int64"),
valid_form("numpy.int64(x:'a) -> numpy.int64 where 'a is numeric")
]
result_typ = builtins.TInt64()
self._unify(node.type, builtins.TInt(),
self._unify(node.type, result_typ,
node.loc, None)
if len(node.args) == 0 and len(node.keywords) == 0:
@ -639,20 +655,7 @@ class Inferencer(algorithm.Visitor):
pass # undetermined yet
elif len(node.args) == 1 and len(node.keywords) == 0 and \
builtins.is_numeric(node.args[0].type):
self._unify(node.type, builtins.TInt(),
node.loc, None)
elif len(node.args) == 1 and len(node.keywords) == 1 and \
builtins.is_numeric(node.args[0].type) and \
node.keywords[0].arg == 'width':
width = node.keywords[0].value
if not (isinstance(width, asttyped.NumT) and isinstance(width.n, int)):
diag = diagnostic.Diagnostic("error",
"the width argument of int() must be an integer literal", {},
node.keywords[0].loc)
self.engine.process(diag)
return
self._unify(node.type, builtins.TInt(types.TValue(width.n)),
self._unify(node.type, result_typ,
node.loc, None)
else:
diagnose(valid_forms())
@ -1049,22 +1052,10 @@ class Inferencer(algorithm.Visitor):
if coerced:
return_type, target_type, value_type = coerced
try:
node.target.type.unify(target_type)
except types.UnificationError as e:
printer = types.TypePrinter()
note = diagnostic.Diagnostic("note",
"expression of type {typec}",
{"typec": printer.name(node.value.type)},
node.value.loc)
diag = diagnostic.Diagnostic("error",
"expression of type {typea} has to be coerced to {typeb}, "
"which makes assignment invalid",
{"typea": printer.name(node.target.type),
"typeb": printer.name(target_type)},
node.op.loc, [node.target.loc], [note])
self.engine.process(diag)
return
if isinstance(node.value, asttyped.CoerceT):
orig_value_type = node.value.value.type
else:
orig_value_type = node.value.type
try:
node.target.type.unify(return_type)
@ -1072,17 +1063,34 @@ class Inferencer(algorithm.Visitor):
printer = types.TypePrinter()
note = diagnostic.Diagnostic("note",
"expression of type {typec}",
{"typec": printer.name(node.value.type)},
{"typec": printer.name(orig_value_type)},
node.value.loc)
diag = diagnostic.Diagnostic("error",
"the result of this operation has type {typeb}, "
"which makes assignment to a slot of type {typea} invalid",
"which cannot be assigned to a left-hand side of type {typea}",
{"typea": printer.name(node.target.type),
"typeb": printer.name(return_type)},
node.op.loc, [node.target.loc], [note])
self.engine.process(diag)
return
try:
node.target.type.unify(target_type)
except types.UnificationError as e:
printer = types.TypePrinter()
note = diagnostic.Diagnostic("note",
"expression of type {typec}",
{"typec": printer.name(orig_value_type)},
node.value.loc)
diag = diagnostic.Diagnostic("error",
"this operation requires the left-hand side of type {typea} "
"to be coerced to {typeb}, which cannot be done",
{"typea": printer.name(node.target.type),
"typeb": printer.name(target_type)},
node.op.loc, [node.target.loc], [note])
self.engine.process(diag)
return
node.value = self._coerce_one(value_type, node.value, other_node=node.target)
def visit_ForT(self, node):

View File

@ -5,7 +5,7 @@ do not.
"""
from pythonparser import algorithm, diagnostic
from .. import types, builtins
from .. import types, builtins, asttyped
class IntMonomorphizer(algorithm.Visitor):
def __init__(self, engine):
@ -35,3 +35,13 @@ class IntMonomorphizer(algorithm.Visitor):
typ = node.type.find()
if types.is_var(typ["width"]):
typ["width"].unify(types.TValue(32))
def visit_CoerceT(self, node):
if isinstance(node.value, asttyped.NumT) and \
builtins.is_int(node.type) and \
builtins.is_int(node.value.type) and \
not types.is_var(node.type["width"]) and \
types.is_var(node.value.type["width"]):
node.value.type.unify(node.type)
self.generic_visit(node)

View File

@ -849,6 +849,8 @@ class LLVMIRGenerator:
def process_Coerce(self, insn):
typ, value_typ = insn.type, insn.value().type
if typ == value_typ:
return self.map(insn.value())
if builtins.is_int(typ) and builtins.is_float(value_typ):
return self.llbuilder.fptosi(self.map(insn.value()), self.llty_of_type(typ),
name=insn.name)
@ -1252,10 +1254,12 @@ class LLVMIRGenerator:
self.llbuilder.call(self.llbuiltin("llvm.stackrestore"), [llstackptr])
# T result = {
# void *ptr = NULL;
# loop: int size = rpc_recv("tag", ptr);
# void *ret_ptr = alloca(sizeof(T));
# void *ptr = ret_ptr;
# loop: int size = recv_rpc(ptr);
# // Non-zero: Provide `size` bytes of extra storage for variable-length data.
# if(size) { ptr = alloca(size); goto loop; }
# else *(T*)ptr
# else *(T*)ret_ptr
# }
llprehead = self.llbuilder.basic_block
llhead = self.llbuilder.append_basic_block(name="rpc.head")
@ -1270,7 +1274,7 @@ class LLVMIRGenerator:
self.llbuilder.branch(llhead)
self.llbuilder.position_at_end(llhead)
llphi = self.llbuilder.phi(llslotgen.type, name="rpc.size")
llphi = self.llbuilder.phi(llslotgen.type, name="rpc.ptr")
llphi.add_incoming(llslotgen, llprehead)
if llunwindblock:
llsize = self.llbuilder.invoke(self.llbuiltin("recv_rpc"), [llphi],

View File

@ -0,0 +1,89 @@
"""
:class:`TypedtreePrinter` prints a human-readable representation of typedtrees.
"""
from pythonparser import algorithm, ast
from .. import types, asttyped
class TypedtreePrinter(algorithm.Visitor):
def __init__(self):
self.str = None
self.level = None
self.last_nl = None
self.type_printer = None
def print(self, node):
try:
self.str = ""
self.level = 0
self.last_nl = 0
self.type_printer = types.TypePrinter()
self.visit(node)
self._nl()
return self.str
finally:
self.str = None
self.level = None
self.last_nl = 0
self.type_printer = None
def _nl(self):
# self.str += "·"
if len(self.str) != self.last_nl:
self.str += "\n" + (" " * self.level)
self.last_nl = len(self.str)
def _indent(self):
self.level += 1
self._nl()
def _dedent(self):
self._nl()
self.level -= 1
self.str = self.str[:-2]
self.last_nl -= 2
def visit(self, obj):
if isinstance(obj, ast.AST):
attrs = set(obj._fields) - {'ctx'}
if isinstance(obj, asttyped.commontyped):
attrs.update(set(obj._types))
for attr in set(attrs):
if not getattr(obj, attr):
attrs.remove(attr) # omit falsey stuff
self.str += obj.__class__.__name__ + "("
if len(attrs) > 1:
self._indent()
for attr in attrs:
if len(attrs) > 1:
self._nl()
self.str += attr + "="
self.visit(getattr(obj, attr))
if len(attrs) > 1:
self._nl()
if len(attrs) > 1:
self._dedent()
self.str += ")"
elif isinstance(obj, types.Type):
self.str += self.type_printer.name(obj, max_depth=0)
elif isinstance(obj, list):
self.str += "["
if len(obj) > 1:
self._indent()
for elem in obj:
if len(obj) > 1:
self._nl()
self.visit(elem)
if len(obj) > 1:
self._nl()
if len(obj) > 1:
self._dedent()
self.str += "]"
else:
self.str += repr(obj)

View File

@ -194,6 +194,9 @@ class TTuple(Type):
def __ne__(self, other):
return not (self == other)
def __hash__(self):
return hash(tuple(self.elts))
class _TPointer(TMono):
def __init__(self):
super().__init__("pointer")

View File

@ -263,7 +263,7 @@ def _extract_log_chars(data):
n = data >> 24
data = (data << 8) & 0xffffffff
if not n:
return r
continue
r += chr(n)
return r

View File

@ -396,11 +396,13 @@ class CommGeneric:
lambda: "bool")
self._write_int8(value)
elif tag == "i":
check(isinstance(value, int) and (-2**31 < value < 2**31-1),
check(isinstance(value, (int, numpy.int32)) and
(-2**31 < value < 2**31-1),
lambda: "32-bit int")
self._write_int32(value)
elif tag == "I":
check(isinstance(value, int) and (-2**63 < value < 2**63-1),
check(isinstance(value, (int, numpy.int32, numpy.int64)) and
(-2**63 < value < 2**63-1),
lambda: "64-bit int")
self._write_int64(value)
elif tag == "f":

View File

@ -81,15 +81,19 @@ class Core:
self.core = self
self.comm.core = self
def compile(self, function, args, kwargs, set_result=None, with_attr_writeback=True):
def compile(self, function, args, kwargs, set_result=None,
attribute_writeback=True, print_as_rpc=True):
try:
engine = _DiagnosticEngine(all_errors_are_fatal=True)
stitcher = Stitcher(engine=engine, core=self, dmgr=self.dmgr)
stitcher = Stitcher(engine=engine, core=self, dmgr=self.dmgr,
print_as_rpc=print_as_rpc)
stitcher.stitch_call(function, args, kwargs, set_result)
stitcher.finalize()
module = Module(stitcher, ref_period=self.ref_period)
module = Module(stitcher,
ref_period=self.ref_period,
attribute_writeback=attribute_writeback)
target = OR1KTarget()
library = target.compile_and_link([module])

View File

@ -1,6 +1,7 @@
from artiq.language.core import *
from artiq.language.types import *
from artiq.language.units import *
from numpy import int64
_PHASE_MODE_DEFAULT = -1
@ -111,20 +112,20 @@ class _DDSGeneric:
"""Returns the frequency tuning word corresponding to the given
frequency.
"""
return round(int(2, width=64)**32*frequency/self.core_dds.sysclk)
return round(float(int64(2)**32*frequency/self.core_dds.sysclk))
@portable(flags=["fast-math"])
def ftw_to_frequency(self, ftw):
"""Returns the frequency corresponding to the given frequency tuning
word.
"""
return ftw*self.core_dds.sysclk/int(2, width=64)**32
return ftw*self.core_dds.sysclk/int64(2)**32
@portable(flags=["fast-math"])
def turns_to_pow(self, turns):
"""Returns the phase offset word corresponding to the given phase
in turns."""
return round(turns*2**self.pow_width)
return round(float(turns*2**self.pow_width))
@portable(flags=["fast-math"])
def pow_to_turns(self, pow):
@ -135,7 +136,7 @@ class _DDSGeneric:
@portable(flags=["fast-math"])
def amplitude_to_asf(self, amplitude):
"""Returns amplitude scale factor corresponding to given amplitude."""
return round(amplitude*0x0fff)
return round(float(amplitude*0x0fff))
@portable(flags=["fast-math"])
def asf_to_amplitude(self, asf):

View File

@ -7,6 +7,7 @@ from PyQt5 import QtCore, QtWidgets
from artiq.tools import short_format
from artiq.gui.tools import LayoutWidget, QRecursiveFilterProxyModel
from artiq.gui.models import DictSyncTreeSepModel
from artiq.gui.scientific_spinbox import ScientificSpinBox
logger = logging.getLogger(__name__)
@ -50,10 +51,10 @@ class Editor(QtWidgets.QDialog):
class NumberEditor(Editor):
def get_edit_widget(self, initial_value):
self.edit_widget = QtWidgets.QDoubleSpinBox()
self.edit_widget.setMinimum(float("-inf"))
self.edit_widget.setMaximum(float("+inf"))
self.edit_widget.setDecimals(8)
self.edit_widget = ScientificSpinBox()
self.edit_widget.setDecimals(13)
self.edit_widget.setPrecision()
self.edit_widget.setRelativeStep()
self.edit_widget.setValue(float(initial_value))
return self.edit_widget

View File

@ -8,7 +8,7 @@ from PyQt5 import QtCore, QtGui, QtWidgets
import h5py
from artiq.gui.tools import LayoutWidget, log_level_to_name, get_open_file_name
from artiq.gui.entries import argty_to_entry, ScanEntry
from artiq.gui.entries import procdesc_to_entry, ScanEntry
from artiq.protocols import pyon
@ -56,7 +56,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
self.viewport().installEventFilter(_WheelFilter(self.viewport()))
self._groups = dict()
self._arg_to_entry_widgetitem = dict()
self._arg_to_widgets = dict()
arguments = self.manager.get_submission_arguments(self.expurl)
@ -68,9 +68,13 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
gradient.setColorAt(0, self.palette().base().color())
gradient.setColorAt(1, self.palette().midlight().color())
for name, argument in arguments.items():
entry = argty_to_entry[argument["desc"]["ty"]](argument)
widgets = dict()
self._arg_to_widgets[name] = widgets
entry = procdesc_to_entry(argument["desc"])(argument)
widget_item = QtWidgets.QTreeWidgetItem([name])
self._arg_to_entry_widgetitem[name] = entry, widget_item
widgets["entry"] = entry
widgets["widget_item"] = widget_item
for col in range(3):
widget_item.setBackground(col, gradient)
@ -83,6 +87,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
else:
self._get_group(argument["group"]).addChild(widget_item)
fix_layout = LayoutWidget()
widgets["fix_layout"] = fix_layout
fix_layout.addWidget(entry)
self.setItemWidget(widget_item, 1, fix_layout)
recompute_argument = QtWidgets.QToolButton()
@ -97,18 +102,20 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
tool_buttons = LayoutWidget()
tool_buttons.addWidget(recompute_argument, 1)
if isinstance(entry, ScanEntry):
disable_other_scans = QtWidgets.QToolButton()
disable_other_scans.setIcon(
QtWidgets.QApplication.style().standardIcon(
QtWidgets.QStyle.SP_DialogResetButton))
disable_other_scans.setToolTip("Disable all other scans in "
"this experiment")
disable_other_scans.clicked.connect(
partial(self._disable_other_scans, name))
tool_buttons.layout.setRowStretch(0, 1)
tool_buttons.layout.setRowStretch(3, 1)
tool_buttons.addWidget(disable_other_scans, 2)
disable_other_scans = QtWidgets.QToolButton()
widgets["disable_other_scans"] = disable_other_scans
disable_other_scans.setIcon(
QtWidgets.QApplication.style().standardIcon(
QtWidgets.QStyle.SP_DialogResetButton))
disable_other_scans.setToolTip("Disable all other scans in "
"this experiment")
disable_other_scans.clicked.connect(
partial(self._disable_other_scans, name))
tool_buttons.layout.setRowStretch(0, 1)
tool_buttons.layout.setRowStretch(3, 1)
tool_buttons.addWidget(disable_other_scans, 2)
if not isinstance(entry, ScanEntry):
disable_other_scans.setVisible(False)
self.setItemWidget(widget_item, 2, tool_buttons)
@ -161,28 +168,41 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
argument = self.manager.get_submission_arguments(self.expurl)[name]
procdesc = arginfo[name][0]
state = argty_to_entry[procdesc["ty"]].default_state(procdesc)
state = procdesc_to_entry(procdesc).default_state(procdesc)
argument["desc"] = procdesc
argument["state"] = state
old_entry, widget_item = self._arg_to_entry_widgetitem[name]
old_entry.deleteLater()
# Qt needs a setItemWidget() to handle layout correctly,
# simply replacing the entry inside the LayoutWidget
# results in a bug.
entry = argty_to_entry[procdesc["ty"]](argument)
self._arg_to_entry_widgetitem[name] = entry, widget_item
self.setItemWidget(widget_item, 1, entry)
widgets = self._arg_to_widgets[name]
widgets["entry"].deleteLater()
widgets["entry"] = procdesc_to_entry(procdesc)(argument)
widgets["disable_other_scans"].setVisible(
isinstance(widgets["entry"], ScanEntry))
widgets["fix_layout"].deleteLater()
widgets["fix_layout"] = LayoutWidget()
widgets["fix_layout"].addWidget(widgets["entry"])
self.setItemWidget(widgets["widget_item"], 1, widgets["fix_layout"])
self.updateGeometries()
def _disable_other_scans(self, current_name):
for name, (entry, _) in self._arg_to_entry_widgetitem.items():
if name != current_name and isinstance(entry, ScanEntry):
entry.disable()
for name, widgets in self._arg_to_widgets.items():
if (name != current_name
and isinstance(widgets["entry"], ScanEntry)):
widgets["entry"].disable()
def save_state(self):
expanded = []
for k, v in self._groups.items():
if v.isExpanded():
expanded.append(k)
return {"expanded": expanded}
return {
"expanded": expanded,
"scroll": self.verticalScrollBar().value()
}
def restore_state(self, state):
for e in state["expanded"]:
@ -190,6 +210,7 @@ class _ArgumentEditor(QtWidgets.QTreeWidget):
self._groups[e].setExpanded(True)
except KeyError:
pass
self.verticalScrollBar().setValue(state["scroll"])
log_levels = ["DEBUG", "INFO", "WARNING", "ERROR", "CRITICAL"]
@ -445,6 +466,7 @@ class ExperimentManager:
self.schedule_ctl = schedule_ctl
self.experiment_db_ctl = experiment_db_ctl
self.dock_states = dict()
self.submission_scheduling = dict()
self.submission_options = dict()
self.submission_arguments = dict()
@ -502,7 +524,7 @@ class ExperimentManager:
def initialize_submission_arguments(self, expurl, arginfo):
arguments = OrderedDict()
for name, (procdesc, group) in arginfo.items():
state = argty_to_entry[procdesc["ty"]].default_state(procdesc)
state = procdesc_to_entry(procdesc).default_state(procdesc)
arguments[name] = {
"desc": procdesc,
"group": group,
@ -539,9 +561,18 @@ class ExperimentManager:
self.main_window.centralWidget().addSubWindow(dock)
dock.show()
dock.sigClosed.connect(partial(self.on_dock_closed, expurl))
if expurl in self.dock_states:
try:
dock.restore_state(self.dock_states[expurl])
except:
logger.warning("Failed to restore dock state when opening "
"experiment %s", expurl,
exc_info=True)
return dock
def on_dock_closed(self, expurl):
dock = self.open_experiments[expurl]
self.dock_states[expurl] = dock.save_state()
del self.open_experiments[expurl]
async def _submit_task(self, expurl, *args):
@ -556,7 +587,7 @@ class ExperimentManager:
argument_values = dict()
for name, argument in arguments.items():
entry_cls = argty_to_entry[argument["desc"]["ty"]]
entry_cls = procdesc_to_entry(argument["desc"])
argument_values[name] = entry_cls.state_to_value(argument["state"])
expid = {
@ -606,6 +637,8 @@ class ExperimentManager:
file, class_name, use_repository = self.resolve_expurl(expurl)
if use_repository:
revision = self.get_submission_options(expurl)["repo_rev"]
else:
revision = None
description = await self.experiment_db_ctl.examine(
file, use_repository, revision)
return description[class_name]["arginfo"]
@ -620,21 +653,22 @@ class ExperimentManager:
self.open_experiment(expurl)
def save_state(self):
docks = {expurl: dock.save_state()
for expurl, dock in self.open_experiments.items()}
for expurl, dock in self.open_experiments.items():
self.dock_states[expurl] = dock.save_state()
return {
"scheduling": self.submission_scheduling,
"options": self.submission_options,
"arguments": self.submission_arguments,
"docks": docks
"docks": self.dock_states,
"open_docks": set(self.open_experiments.keys())
}
def restore_state(self, state):
if self.open_experiments:
raise NotImplementedError
self.dock_states = state["docks"]
self.submission_scheduling = state["scheduling"]
self.submission_options = state["options"]
self.submission_arguments = state["arguments"]
for expurl, dock_state in state["docks"].items():
dock = self.open_experiment(expurl)
dock.restore_state(dock_state)
for expurl in state["open_docks"]:
self.open_experiment(expurl)

View File

@ -207,6 +207,10 @@ class _DeviceManager:
widget = None
if v["module"] == "artiq.coredevice.ttl":
channel = v["arguments"]["channel"]
if channel > 63:
# The moninj protocol is limited to 64 channels; ignore
# any beyond that for now to avoid confusion.
return
force_out = v["class"] == "TTLOut"
widget = _TTLWidget(
channel, self.send_to_device, force_out, k)

View File

@ -177,7 +177,8 @@ class Novatech409B:
"00989680 2000 01F5 0000 00000000 00000000 000301",
"80 BC0000 0000 0102 21"]
else:
self.port.reset_input_buffer()
self.port.ser.reset_input_buffer()
result = []
await self.port.write(("QUE" + "\r\n").encode())
for i in range(5):
m = (await self._ser_readline()).rstrip().decode()

View File

@ -13,6 +13,7 @@ from prettytable import PrettyTable
from artiq.protocols.pc_rpc import Client
from artiq.protocols.sync_struct import Subscriber
from artiq.protocols.broadcast import Receiver
from artiq.protocols import pyon
from artiq.tools import short_format
@ -236,8 +237,6 @@ def _show_datasets(datasets):
def _run_subscriber(host, port, subscriber):
if port is None:
port = 3250
loop = asyncio.get_event_loop()
try:
loop.run_until_complete(subscriber.connect(host, port))
@ -259,7 +258,8 @@ def _show_dict(args, notifier_name, display_fun):
return d
subscriber = Subscriber(notifier_name, init_d,
lambda mod: display_fun(d))
_run_subscriber(args.server, args.port, subscriber)
port = 3250 if args.port is None else args.port
_run_subscriber(args.server, port, subscriber)
def _print_log_record(record):
@ -268,30 +268,10 @@ def _print_log_record(record):
print(level, source, t, message)
class _LogPrinter:
def __init__(self, init):
for record in init:
_print_log_record(record)
def append(self, record):
_print_log_record(record)
def insert(self, i, record):
_print_log_record(record)
def pop(self, i=-1):
pass
def __delitem__(self, x):
pass
def __setitem__(self, k, v):
pass
def _show_log(args):
subscriber = Subscriber("log", _LogPrinter)
_run_subscriber(args.server, args.port, subscriber)
subscriber = Receiver("log", [_print_log_record])
port = 1067 if args.port is None else args.port
_run_subscriber(args.server, port, subscriber)
def main():

View File

@ -55,7 +55,7 @@ def main():
object_map, kernel_library, _, _ = \
core.compile(exp.run, [exp_inst], {},
with_attr_writeback=False)
attribute_writeback=False, print_as_rpc=False)
except CompileError as error:
return
finally:

View File

@ -11,12 +11,14 @@ from artiq import __artiq_dir__ as artiq_dir
from artiq.frontend.bit2bin import bit2bin
scripts_path = ["share", "openocd", "scripts"]
if os.name == "nt":
scripts_path.insert(0, "Library")
scripts_path = os.path.abspath(os.path.join(
os.path.dirname(shutil.which("openocd")),
"..", *scripts_path))
def scripts_path():
p = ["share", "openocd", "scripts"]
if os.name == "nt":
p.insert(0, "Library")
p = os.path.abspath(os.path.join(
os.path.dirname(shutil.which("openocd")),
"..", *p))
return p
def get_argparser():
@ -139,7 +141,7 @@ def main():
target_file = opts.target_file
subprocess.check_call([
"openocd",
"-s", scripts_path,
"-s", scripts_path(),
"-f", target_file,
"-c", "; ".join(prog),
])

View File

@ -1,22 +1,7 @@
#!/usr/bin/env python3.5
# Copyright 2014-2015 Robert Jordens <jordens@gmail.com>
# Copyright 2014-2017 Robert Jordens <jordens@gmail.com>
# after
# https://github.com/mfischer/fpgadev-zynq/blob/master/top/python/bit_to_zynq_bin.py
#
# This file is part of redpid.
#
# redpid is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# redpid is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with redpid. If not, see <http://www.gnu.org/licenses/>.
import struct

View File

@ -5,6 +5,7 @@
import argparse
import logging
import sys
import os
import asyncio
from artiq.devices.novatech409b.driver import Novatech409B
@ -33,6 +34,9 @@ def main():
args = get_argparser().parse_args()
init_logger(args)
if os.name == "nt":
asyncio.set_event_loop(asyncio.ProactorEventLoop())
if not args.simulation and args.device is None:
print("You need to specify either --simulation or -d/--device "
"argument. Use --help for more information.")

View File

@ -2,6 +2,8 @@
import argparse
import sys
import os
import asyncio
from artiq.devices.thorlabs_tcube.driver import Tdc, Tpz, TdcSim, TpzSim
from artiq.protocols.pc_rpc import simple_server_loop
@ -28,6 +30,9 @@ def main():
args = get_argparser().parse_args()
init_logger(args)
if os.name == "nt":
asyncio.set_event_loop(asyncio.ProactorEventLoop())
if not args.simulation and args.device is None:
print("You need to specify either --simulation or -d/--device "
"argument. Use --help for more information.")

View File

@ -153,8 +153,8 @@ class _OutputManager(Module):
# Note: replace may be asserted at the same time as collision
# when addresses are different. In that case, it is a collision.
self.sync.rsys += replace.eq(self.ev.timestamp == buf.timestamp)
# Detect sequence errors on coarse timestamps only
# so that they are mutually exclusive with collision errors.
# Detect sequence errors on coarse timestamps only
# so that they are mutually exclusive with collision errors.
self.sync.rsys += sequence_error.eq(self.ev.timestamp[fine_ts_width:] <
buf.timestamp[fine_ts_width:])
if interface.enable_replace:
@ -167,6 +167,9 @@ class _OutputManager(Module):
(self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
& ((self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
|different_addresses))
else:
self.sync.rsys += collision.eq(
(self.ev.timestamp == buf.timestamp) & different_addresses)
else:
self.sync.rsys += collision.eq(
self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])

View File

@ -1,163 +1,8 @@
from itertools import product
from migen import *
from migen.genlib.fsm import FSM, NextState
from misoc.interconnect import wishbone
class SPIClockGen(Module):
def __init__(self, width):
self.load = Signal(width)
self.bias = Signal() # bias this clock phase to longer times
self.edge = Signal()
self.clk = Signal(reset=1)
cnt = Signal.like(self.load)
bias = Signal()
zero = Signal()
self.comb += [
zero.eq(cnt == 0),
self.edge.eq(zero & ~bias),
]
self.sync += [
If(zero,
bias.eq(0),
).Else(
cnt.eq(cnt - 1),
),
If(self.edge,
cnt.eq(self.load[1:]),
bias.eq(self.load[0] & (self.clk ^ self.bias)),
self.clk.eq(~self.clk),
)
]
class SPIRegister(Module):
def __init__(self, width):
self.data = Signal(width)
self.o = Signal()
self.i = Signal()
self.lsb = Signal()
self.shift = Signal()
self.sample = Signal()
self.comb += [
self.o.eq(Mux(self.lsb, self.data[0], self.data[-1])),
]
self.sync += [
If(self.shift,
If(self.lsb,
self.data[:-1].eq(self.data[1:]),
).Else(
self.data[1:].eq(self.data[:-1]),
)
),
If(self.sample,
If(self.lsb,
self.data[-1].eq(self.i),
).Else(
self.data[0].eq(self.i),
)
)
]
class SPIBitCounter(Module):
def __init__(self, width):
self.n_read = Signal(width)
self.n_write = Signal(width)
self.read = Signal()
self.write = Signal()
self.done = Signal()
self.comb += [
self.write.eq(self.n_write != 0),
self.read.eq(self.n_read != 0),
self.done.eq(~(self.write | self.read)),
]
self.sync += [
If(self.write,
self.n_write.eq(self.n_write - 1),
).Elif(self.read,
self.n_read.eq(self.n_read - 1),
)
]
class SPIMachine(Module):
def __init__(self, data_width, clock_width, bits_width):
ce = CEInserter()
self.submodules.cg = ce(SPIClockGen(clock_width))
self.submodules.reg = ce(SPIRegister(data_width))
self.submodules.bits = ce(SPIBitCounter(bits_width))
self.div_write = Signal.like(self.cg.load)
self.div_read = Signal.like(self.cg.load)
self.clk_phase = Signal()
self.start = Signal()
self.cs = Signal()
self.oe = Signal()
self.done = Signal()
# # #
fsm = CEInserter()(FSM("IDLE"))
self.submodules += fsm
fsm.act("IDLE",
If(self.start,
If(self.clk_phase,
NextState("WAIT"),
).Else(
NextState("SETUP"),
)
)
)
fsm.act("SETUP",
self.reg.sample.eq(1),
NextState("HOLD"),
)
fsm.act("HOLD",
If(self.bits.done & ~self.start,
If(self.clk_phase,
NextState("IDLE"),
).Else(
NextState("WAIT"),
)
).Else(
self.reg.shift.eq(~self.start),
NextState("SETUP"),
)
)
fsm.act("WAIT",
If(self.bits.done,
NextState("IDLE"),
).Else(
NextState("SETUP"),
)
)
write0 = Signal()
self.sync += [
If(self.cg.edge & self.reg.shift,
write0.eq(self.bits.write),
)
]
self.comb += [
self.cg.ce.eq(self.start | self.cs | ~self.cg.edge),
If(self.bits.write | ~self.bits.read,
self.cg.load.eq(self.div_write),
).Else(
self.cg.load.eq(self.div_read),
),
self.cg.bias.eq(self.clk_phase),
fsm.ce.eq(self.cg.edge),
self.cs.eq(~fsm.ongoing("IDLE")),
self.reg.ce.eq(self.cg.edge),
self.bits.ce.eq(self.cg.edge & self.reg.sample),
self.done.eq(self.cg.edge & self.bits.done & fsm.ongoing("HOLD")),
self.oe.eq(write0 | self.bits.write),
]
from misoc.cores.spi.core import SPIMachine
class SPIMaster(Module):
@ -293,7 +138,7 @@ class SPIMaster(Module):
assert len(xfer) <= len(bus.dat_w)
self.submodules.spi = spi = SPIMachine(
data_width=len(bus.dat_w),
data_width=len(bus.dat_w) + 1,
clock_width=len(config.div_read),
bits_width=len(xfer.read_length))
@ -311,13 +156,18 @@ class SPIMaster(Module):
]
self.sync += [
If(spi.done,
data_read.eq(spi.reg.data),
data_read.eq(
Mux(spi.reg.lsb, spi.reg.data[1:], spi.reg.data[:-1])),
),
If(spi.start,
cs.eq(xfer.cs),
spi.bits.n_write.eq(xfer.write_length),
spi.bits.n_read.eq(xfer.read_length),
spi.reg.data.eq(data_write),
If(spi.reg.lsb,
spi.reg.data[:-1].eq(data_write),
).Else(
spi.reg.data[1:].eq(data_write),
),
pending.eq(0),
),
# wb.ack a transaction if any of the following:

View File

@ -248,16 +248,16 @@ class NIST_CLOCK(_NIST_Ions):
if i % 4 == 3:
phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=1024))
else:
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=1024))
for i in range(2):
phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16384))
phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
self.submodules += phy
@ -297,7 +297,7 @@ class NIST_CLOCK(_NIST_Ions):
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512,
ofifo_depth=16384,
ififo_depth=4))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)

View File

@ -176,7 +176,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
self.rtio_crg.rtiox4_stb)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256,
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128,
ofifo_depth=4))
# the last TTL is used for ClockGen
@ -223,7 +223,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
phy = dds.AD9858(dds_pins, 8)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=256,
ofifo_depth=128,
ififo_depth=4))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)

View File

@ -81,13 +81,14 @@ class AppletIPCServer(AsyncioParentComm):
finally:
self.datasets_sub.notify_cbs.remove(self._on_mod)
def start(self, embed_cb, fix_initial_size_cb):
def start_server(self, embed_cb, fix_initial_size_cb):
self.server_task = asyncio.ensure_future(
self.serve(embed_cb, fix_initial_size_cb))
async def stop(self):
self.server_task.cancel()
await asyncio.wait([self.server_task])
async def stop_server(self):
if hasattr(self, "server_task"):
self.server_task.cancel()
await asyncio.wait([self.server_task])
class _AppletDock(QDockWidgetCloseDetect):
@ -137,13 +138,14 @@ class _AppletDock(QDockWidgetCloseDetect):
except:
logger.warning("Applet %s failed to start", self.applet_name,
exc_info=True)
return
asyncio.ensure_future(
LogParser(self._get_log_source).stream_task(
self.ipc.process.stdout))
asyncio.ensure_future(
LogParser(self._get_log_source).stream_task(
self.ipc.process.stderr))
self.ipc.start(self.embed, self.fix_initial_size)
self.ipc.start_server(self.embed, self.fix_initial_size)
finally:
self.starting_stopping = False
@ -165,18 +167,19 @@ class _AppletDock(QDockWidgetCloseDetect):
self.starting_stopping = True
if hasattr(self, "ipc"):
await self.ipc.stop()
self.ipc.write_pyon({"action": "terminate"})
try:
await asyncio.wait_for(self.ipc.process.wait(), 2.0)
except:
logger.warning("Applet %s failed to exit, killing",
self.applet_name)
await self.ipc.stop_server()
if hasattr(self.ipc, "process"):
self.ipc.write_pyon({"action": "terminate"})
try:
self.ipc.process.kill()
except ProcessLookupError:
pass
await self.ipc.process.wait()
await asyncio.wait_for(self.ipc.process.wait(), 2.0)
except:
logger.warning("Applet %s failed to exit, killing",
self.applet_name)
try:
self.ipc.process.kill()
except ProcessLookupError:
pass
await self.ipc.process.wait()
del self.ipc
if hasattr(self, "embed_widget"):

View File

@ -69,7 +69,41 @@ class EnumerationEntry(QtWidgets.QComboBox):
return procdesc["choices"][0]
class NumberEntry(ScientificSpinBox):
class NumberEntryInt(QtWidgets.QSpinBox):
def __init__(self, argument):
QtWidgets.QSpinBox.__init__(self)
disable_scroll_wheel(self)
procdesc = argument["desc"]
self.setSingleStep(procdesc["step"])
if procdesc["min"] is not None:
self.setMinimum(procdesc["min"])
else:
self.setMinimum(-((1 << 31) - 1))
if procdesc["max"] is not None:
self.setMaximum(procdesc["max"])
else:
self.setMaximum((1 << 31) - 1)
if procdesc["unit"]:
self.setSuffix(" " + procdesc["unit"])
self.setValue(argument["state"])
def update(value):
argument["state"] = value
self.valueChanged.connect(update)
@staticmethod
def state_to_value(state):
return state
@staticmethod
def default_state(procdesc):
if "default" in procdesc:
return procdesc["default"]
else:
return 0
class NumberEntryFloat(ScientificSpinBox):
def __init__(self, argument):
ScientificSpinBox.__init__(self)
disable_scroll_wheel(self)
@ -136,6 +170,19 @@ class _NoScan(LayoutWidget):
state["value"] = value*scale
self.value.valueChanged.connect(update)
self.repetitions = QtWidgets.QSpinBox()
self.repetitions.setMinimum(1)
self.repetitions.setMaximum((1 << 31) - 1)
disable_scroll_wheel(self.repetitions)
self.addWidget(QtWidgets.QLabel("Repetitions:"), 1, 0)
self.addWidget(self.repetitions, 1, 1)
self.repetitions.setValue(state["repetitions"])
def update_repetitions(value):
state["repetitions"] = value
self.repetitions.valueChanged.connect(update_repetitions)
class _RangeScan(LayoutWidget):
def __init__(self, procdesc, state):
@ -272,6 +319,7 @@ class ScanEntry(LayoutWidget):
def disable(self):
self.radiobuttons["NoScan"].setChecked(True)
self.widgets["NoScan"].repetitions.setValue(1)
@staticmethod
def state_to_value(state):
@ -285,7 +333,7 @@ class ScanEntry(LayoutWidget):
scale = procdesc["scale"]
state = {
"selected": "NoScan",
"NoScan": {"value": 0.0},
"NoScan": {"value": 0.0, "repetitions": 1},
"LinearScan": {"start": 0.0, "stop": 100.0*scale, "npoints": 10},
"RandomScan": {"start": 0.0, "stop": 100.0*scale, "npoints": 10},
"ExplicitScan": {"sequence": []}
@ -299,6 +347,7 @@ class ScanEntry(LayoutWidget):
ty = default["ty"]
if ty == "NoScan":
state[ty]["value"] = default["value"]
state[ty]["repetitions"] = default["repetitions"]
elif ty == "LinearScan" or ty == "RandomScan":
state[ty]["start"] = default["start"]
state[ty]["stop"] = default["stop"]
@ -317,11 +366,21 @@ class ScanEntry(LayoutWidget):
break
argty_to_entry = {
"PYONValue": StringEntry,
"BooleanValue": BooleanEntry,
"EnumerationValue": EnumerationEntry,
"NumberValue": NumberEntry,
"StringValue": StringEntry,
"Scannable": ScanEntry
}
def procdesc_to_entry(procdesc):
ty = procdesc["ty"]
if ty == "NumberValue":
is_int = (procdesc["ndecimals"] == 0
and int(procdesc["step"]) == procdesc["step"]
and procdesc["scale"] == 1)
if is_int:
return NumberEntryInt
else:
return NumberEntryFloat
else:
return {
"PYONValue": StringEntry,
"BooleanValue": BooleanEntry,
"EnumerationValue": EnumerationEntry,
"StringValue": StringEntry,
"Scannable": ScanEntry
}[ty]

View File

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After

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View File

@ -48,6 +48,12 @@ class _SimpleArgProcessor:
class PYONValue(_SimpleArgProcessor):
"""An argument that can be any PYON-serializable value."""
def __init__(self, default=NoDefault):
# Override the _SimpleArgProcessor init, as list defaults are valid
# PYON values
if default is not NoDefault:
self.default_value = default
def process(self, x):
return pyon.decode(x)

View File

@ -36,23 +36,27 @@ class ScanObject:
class NoScan(ScanObject):
"""A scan object that yields a single value."""
def __init__(self, value):
"""A scan object that yields a single value for a specified number
of repetitions."""
def __init__(self, value, repetitions=1):
self.value = value
self.repetitions = repetitions
@portable
def _gen(self):
yield self.value
for i in range(self.repetitions):
yield self.value
@portable
def __iter__(self):
return self._gen()
def __len__(self):
return 1
return self.repetitions
def describe(self):
return {"ty": "NoScan", "value": self.value}
return {"ty": "NoScan", "value": self.value,
"repetitions": self.repetitions}
class LinearScan(ScanObject):
@ -99,7 +103,7 @@ class RandomScan(ScanObject):
if seed is None:
rf = random.random
else:
rf = Random(seed).random
rf = random.Random(seed).random
random.shuffle(self.sequence, rf)
@portable

View File

@ -2,6 +2,7 @@ import asyncio
import os
import tempfile
import shutil
import time
import logging
from artiq.protocols.sync_struct import Notifier
@ -13,60 +14,71 @@ from artiq.tools import get_windows_drives, exc_to_warning
logger = logging.getLogger(__name__)
async def _get_repository_entries(entry_dict,
root, filename, worker_handlers):
worker = Worker(worker_handlers)
try:
description = await worker.examine("scan", os.path.join(root, filename))
except:
log_worker_exception()
raise
finally:
await worker.close()
for class_name, class_desc in description.items():
name = class_desc["name"]
arginfo = class_desc["arginfo"]
if "/" in name:
logger.warning("Character '/' is not allowed in experiment "
"name (%s)", name)
name = name.replace("/", "_")
if name in entry_dict:
basename = name
i = 1
while name in entry_dict:
name = basename + str(i)
i += 1
logger.warning("Duplicate experiment name: '%s'\n"
"Renaming class '%s' in '%s' to '%s'",
basename, class_name, filename, name)
entry = {
"file": filename,
"class_name": class_name,
"arginfo": arginfo
}
entry_dict[name] = entry
class _RepoScanner:
def __init__(self, worker_handlers):
self.worker_handlers = worker_handlers
self.worker = None
async def process_file(self, entry_dict, root, filename):
logger.debug("processing file %s %s", root, filename)
try:
description = await self.worker.examine(
"scan", os.path.join(root, filename))
except:
log_worker_exception()
raise
for class_name, class_desc in description.items():
name = class_desc["name"]
arginfo = class_desc["arginfo"]
if "/" in name:
logger.warning("Character '/' is not allowed in experiment "
"name (%s)", name)
name = name.replace("/", "_")
if name in entry_dict:
basename = name
i = 1
while name in entry_dict:
name = basename + str(i)
i += 1
logger.warning("Duplicate experiment name: '%s'\n"
"Renaming class '%s' in '%s' to '%s'",
basename, class_name, filename, name)
entry = {
"file": filename,
"class_name": class_name,
"arginfo": arginfo
}
entry_dict[name] = entry
async def _scan_experiments(root, worker_handlers, subdir=""):
entry_dict = dict()
for de in os.scandir(os.path.join(root, subdir)):
if de.name.startswith("."):
continue
if de.is_file() and de.name.endswith(".py"):
filename = os.path.join(subdir, de.name)
try:
await _get_repository_entries(
entry_dict, root, filename, worker_handlers)
except Exception as exc:
logger.warning("Skipping file '%s'", filename,
exc_info=not isinstance(exc, WorkerInternalException))
if de.is_dir():
subentries = await _scan_experiments(
root, worker_handlers,
os.path.join(subdir, de.name))
entries = {de.name + "/" + k: v for k, v in subentries.items()}
entry_dict.update(entries)
return entry_dict
async def _scan(self, root, subdir=""):
entry_dict = dict()
for de in os.scandir(os.path.join(root, subdir)):
if de.name.startswith("."):
continue
if de.is_file() and de.name.endswith(".py"):
filename = os.path.join(subdir, de.name)
try:
await self.process_file(entry_dict, root, filename)
except Exception as exc:
logger.warning("Skipping file '%s'", filename,
exc_info=not isinstance(exc, WorkerInternalException))
# restart worker
await self.worker.close()
self.worker = Worker(self.worker_handlers)
if de.is_dir():
subentries = await self._scan(
root, os.path.join(subdir, de.name))
entries = {de.name + "/" + k: v for k, v in subentries.items()}
entry_dict.update(entries)
return entry_dict
async def scan(self, root):
self.worker = Worker(self.worker_handlers)
try:
r = await self._scan(root)
finally:
await self.worker.close()
return r
def _sync_explist(target, source):
@ -109,7 +121,9 @@ class ExperimentDB:
self.repo_backend.release_rev(self.cur_rev)
self.cur_rev = new_cur_rev
self.status["cur_rev"] = new_cur_rev
new_explist = await _scan_experiments(wd, self.worker_handlers)
t1 = time.monotonic()
new_explist = await _RepoScanner(self.worker_handlers).scan(wd)
logger.info("repository scan took %d seconds", time.monotonic()-t1)
_sync_explist(self.explist, new_explist)
finally:

View File

@ -446,6 +446,9 @@ class Scheduler:
whether returning control to the host and pausing would have an effect,
in order to avoid the cost of switching kernels in the common case
where ``pause`` does nothing.
This function does not have side effects, and does not have to be
followed by a call to ``pause``.
"""
for pipeline in self._pipelines.values():
if rid in pipeline.pool.runs:

View File

@ -76,6 +76,8 @@ class Worker:
return "worker({},{})".format(self.rid, self.filename)
async def _create_process(self, log_level):
if self.ipc is not None:
return # process already exists, recycle
await self.io_lock.acquire()
try:
if self.closed.is_set():

View File

@ -190,14 +190,20 @@ class DatasetManager:
broadcast = True
if broadcast:
self.broadcast[key] = persist, value
elif key in self.broadcast.read:
del self.broadcast[key]
if save:
self.local[key] = value
elif key in self.local:
del self.local[key]
def mutate(self, key, index, value):
target = None
if key in self.local:
target = self.local[key]
if key in self.broadcast.read:
if target is not None:
assert target is self.broadcast.read[key][1]
target = self.broadcast[key][1]
if target is None:
raise KeyError("Cannot mutate non-existing dataset")

View File

@ -4,7 +4,7 @@ import sys
__all__ = []
if sys.version_info[:3] == (3, 5, 2):
if sys.version_info[:3] >= (3, 5, 2):
import asyncio
# See https://github.com/m-labs/artiq/issues/506

View File

@ -17,7 +17,7 @@ class Receiver:
async def connect(self, host, port):
self.reader, self.writer = \
await asyncio.open_connection(host, port, limit=4*1024*1024)
await asyncio.open_connection(host, port, limit=100*1024*1024)
try:
self.writer.write(_init_string)
self.writer.write((self.name + "\n").encode())

View File

@ -201,7 +201,7 @@ class AsyncioClient:
this method is a coroutine. See ``Client`` for a description of the
parameters."""
self.__reader, self.__writer = \
await asyncio.open_connection(host, port, limit=4*1024*1024)
await asyncio.open_connection(host, port, limit=100*1024*1024)
try:
self.__writer.write(_init_string)
server_identification = await self.__recv()

View File

@ -64,7 +64,7 @@ class Subscriber:
async def connect(self, host, port, before_receive_cb=None):
self.reader, self.writer = \
await asyncio.open_connection(host, port, limit=4*1024*1024)
await asyncio.open_connection(host, port, limit=100*1024*1024)
try:
if before_receive_cb is not None:
before_receive_cb()

View File

@ -97,6 +97,7 @@ static const struct symbol runtime_exports[] = {
{"__artiq_raise", &__artiq_raise},
{"__artiq_reraise", &__artiq_reraise},
{"strcmp", &strcmp},
{"strlen", &strlen},
{"abort", &ksupport_abort},
/* proxified syscalls */

View File

@ -12,6 +12,8 @@
#include "log.h"
#include "moninj.h"
#define min(a, b) (a>b?b:a)
enum {
MONINJ_REQ_MONITOR = 1,
MONINJ_REQ_TTLSET = 2
@ -52,7 +54,8 @@ static void moninj_monitor(const ip_addr_t *addr, u16_t port)
reply.ttl_levels = 0;
reply.ttl_oes = 0;
reply.ttl_overrides = 0;
for(i=0;i<CONFIG_RTIO_REGULAR_TTL_COUNT;i++) {
/* send at most 64 channels, the protocol doesn't support more */
for(i=0;i<min(CONFIG_RTIO_REGULAR_TTL_COUNT, 64);i++) {
rtio_moninj_mon_chan_sel_write(i);
rtio_moninj_mon_probe_sel_write(0);
rtio_moninj_mon_value_update_write(1);

View File

@ -249,6 +249,19 @@ class Handover(EnvExperiment):
self.k("t2")
class Rounding(EnvExperiment):
def build(self):
self.setattr_device("core")
@kernel
def run(self):
self.core.reset()
t1 = now_mu()
delay(8*us)
t2 = now_mu()
self.set_dataset("delta", t2 - t1)
class DummyException(Exception):
pass
@ -353,6 +366,11 @@ class CoredeviceTest(ExperimentCase):
self.assertEqual(self.dataset_mgr.get("t1") + 1234,
self.dataset_mgr.get("t2"))
def test_rounding(self):
self.execute(Rounding)
dt = self.dataset_mgr.get("delta")
self.assertEqual(dt, 8000)
class RPCTiming(EnvExperiment):

View File

@ -0,0 +1,9 @@
# RUN: %python -m artiq.compiler.testbench.signature +diag %s >%t
# RUN: OutputCheck %s --file-to-check=%t
# CHECK-L: ${LINE:+1}: error: this function must return a value of type numpy.int32 explicitly
def foo(x):
if x:
return 1
foo(True)

View File

@ -0,0 +1,4 @@
# RUN: %python -m artiq.compiler.testbench.llvmgen %s
def f():
return float(1.0)

View File

@ -0,0 +1,9 @@
# RUN: %python -m artiq.compiler.testbench.signature %s
def foo(x):
if x:
return 1
else:
return 2
foo(True)

View File

@ -0,0 +1,22 @@
# RUN: %python -m artiq.compiler.testbench.embedding %s
from artiq.language.core import *
from artiq.language.types import *
class a:
def foo(self, x):
print(x)
class b:
def __init__(self):
self.obj = a()
self.meth = self.obj.foo
@kernel
def run(self):
self.meth(1)
bi = b()
@kernel
def entrypoint():
bi.run()

View File

@ -0,0 +1,20 @@
# RUN: %python -m artiq.compiler.testbench.embedding +diag %s 2>%t
# RUN: OutputCheck %s --file-to-check=%t
from artiq.language.core import *
from artiq.language.types import *
class c:
kernel_invariants = {"a", "b"}
a = 0
def __repr__(self):
return "<testbench.c object>"
i = c()
@kernel
def entrypoint():
# CHECK-L: <synthesized>:1: warning: object <testbench.c object> of type <instance testbench.c> declares attribute 'b' as kernel invariant, but the instance referenced here does not have this attribute
# CHECK-L: ${LINE:+1}: note: expanded from here
i

View File

@ -13,8 +13,8 @@ int()
# CHECK-L: int:<constructor int>(1.0:float):numpy.int?
int(1.0)
# CHECK-L: int:<constructor int>(1.0:float, width=64:numpy.int?):numpy.int64
int(1.0, width=64)
# CHECK-L: int64:<function int64>(1.0:float):numpy.int64
int64(1.0)
# CHECK-L: float:<constructor float {}>():float
float()

View File

@ -0,0 +1,5 @@
# RUN: %python -m artiq.compiler.testbench.inferencer +mono %s >%t
# RUN: OutputCheck %s --file-to-check=%t
# CHECK-L: numpy.int64
int64(2)**32

View File

@ -1,10 +1,6 @@
# RUN: %python -m artiq.compiler.testbench.inferencer +diag %s >%t
# RUN: OutputCheck %s --file-to-check=%t
a = 1
# CHECK-L: ${LINE:+1}: error: the width argument of int() must be an integer literal
int(1.0, width=a)
# CHECK-L: ${LINE:+1}: error: the argument of len() must be of an iterable type
len(1)

View File

@ -28,10 +28,10 @@
# CHECK-L: ${LINE:+1}: error: cannot coerce list(elt='a) to a numeric type
[] - 1.0
# CHECK-L: ${LINE:+2}: error: expression of type numpy.int? has to be coerced to float, which makes assignment invalid
# CHECK-L: ${LINE:+2}: error: the result of this operation has type float, which cannot be assigned to a left-hand side of type numpy.int?
# CHECK-L: ${LINE:+1}: note: expression of type float
a = 1; a += 1.0
# CHECK-L: ${LINE:+2}: error: the result of this operation has type (numpy.int?, float), which makes assignment to a slot of type (numpy.int?,) invalid
# CHECK-L: ${LINE:+2}: error: the result of this operation has type (numpy.int?, float), which cannot be assigned to a left-hand side of type (numpy.int?,)
# CHECK-L: ${LINE:+1}: note: expression of type (float,)
b = (1,); b += (1.0,)

View File

@ -7,7 +7,7 @@ assert bool() is False
assert int() is 0
assert int(1.0) is 1
#ARTIQ#assert int(1, width=64) << 40 is 1099511627776
#ARTIQ#assert int64(1) << 40 is 1099511627776
#ARTIQ#assert float() is 0.0
#ARTIQ#assert float(1) is 1.0

View File

@ -27,3 +27,27 @@ for x in range(10):
assert False
else:
assert False
# Verify continue target is reset in else block.
cond = False
while True:
if cond:
break
cond = True
for _ in range(1):
pass
else:
continue
assert False
else:
assert False
# Verify for target is reset in else block.
while True:
for _ in range(1):
pass
else:
break
assert False
else:
assert False

View File

@ -29,3 +29,27 @@ while cond:
cond = False
continue
assert False
# Verify continue target is reset in else block.
cond = False
while True:
if cond:
break
cond = True
while False:
assert False
else:
continue
assert False
else:
assert False
# Verify break target is reset in else block.
while True:
while False:
assert False
else:
break
assert False
else:
assert False

View File

@ -0,0 +1,10 @@
# RUN: %python -m artiq.compiler.testbench.signature %s >%t
# RUN: OutputCheck %s --file-to-check=%t
def f(x):
x = int64(0)
return x
# CHECK-L: g: ()->numpy.int64
def g():
return f(1 + 0)

View File

@ -0,0 +1,17 @@
# RUN: %python -m artiq.compiler.testbench.embedding %s
from artiq.language.core import *
from artiq.language.types import *
import numpy as np
@kernel
def rotate(array):
'''Rotates an array, deleting the oldest value'''
length = len(array)
for i in range(np.int64(len(array)) - 1):
array[length - i - 1] = array[length - i - 2]
array[0] = 0
@kernel
def entrypoint():
rotate([1,2,3,4])

View File

@ -0,0 +1,14 @@
{
"comm": {
"type": "local",
"module": "artiq.coredevice.comm_dummy",
"class": "Comm",
"arguments": {}
},
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"ref_period": 1e-9}
}
}

9
conda/artiq-dev.yaml Normal file
View File

@ -0,0 +1,9 @@
# conda description for an environment to build and develop artiq
# $ conda env create -f conda/artiq-dev.yml
name: artiq-dev
channels:
- m-labs/label/main
- m-labs/label/dev
- defaults
dependencies:
- artiq-dev

47
conda/artiq-dev/meta.yaml Normal file
View File

@ -0,0 +1,47 @@
package:
name: artiq-dev
version: {{ environ.get("GIT_DESCRIBE_TAG", "") }}
source:
git_url: ../..
build:
noarch_python: true
number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:12] }}
requirements:
run:
- python 3.5.2
- setuptools
- migen 0.4
- misoc 0.3
- binutils-or1k-linux
- llvm-or1k
- llvmlite-artiq 0.10.0.dev py35_24
- openocd >=0.10
- lit
- outputcheck
- coverage
- scipy
- numpy
- prettytable
- asyncserial
- sphinx 1.4.8
- sphinx-argparse
- sphinxcontrib-wavedrom
- sphinx_rtd_theme
- h5py
- dateutil
- pyqt >=5.5
- quamash
- pyqtgraph
- pygit2
- aiohttp
- pythonparser 1.0
- levenshtein
about:
home: https://m-labs.hk/artiq
license: GPL
summary: 'ARTIQ development metapackage'

14
conda/artiq-doc.yaml Normal file
View File

@ -0,0 +1,14 @@
# conda description for an environment to build artiq documentation
# $ conda env create -f conda/artiq-doc.yml
name: artiq-doc
channels:
- m-labs/label/dev
- m-labs/label/main
- defaults
dependencies:
- python=3.5.2
- sphinx=1.4.8
- sphinx-argparse
- sphinxcontrib-wavedrom
- sphinx_rtd_theme
- pythonparser=1.0

View File

@ -8,18 +8,15 @@ source:
build:
noarch_python: true
number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:12] }}
requirements:
build:
- migen 0.2
- misoc 0.2
- llvm-or1k
- binutils-or1k-linux
- artiq-dev {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:12]) if "GIT_DESCRIBE_TAG" in environ else "" }}
run:
- artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_DESCRIBE_HASH")[1:]) if "GIT_DESCRIBE_TAG" in environ else "" }}
- artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:12]) if "GIT_DESCRIBE_TAG" in environ else "" }}
about:
home: https://m-labs.hk/artiq
license: GPL
summary: 'Bitstream, BIOS and runtime for NIST_QC2 on the KC705 board'
summary: 'Bitstream, BIOS and runtime for NIST_CLOCK on the KC705 board'

View File

@ -1,14 +0,0 @@
#!/bin/bash
BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
[ -f $BUILD_SETTINGS_FILE ] && . $BUILD_SETTINGS_FILE
SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-nist_qc1
mkdir -p $SOC_PREFIX
$PYTHON -m artiq.gateware.targets.kc705 -H nist_qc1 --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
cp misoc_nist_qc1_kc705/gateware/top.bit $SOC_PREFIX
cp misoc_nist_qc1_kc705/software/bios/bios.bin $SOC_PREFIX
cp misoc_nist_qc1_kc705/software/runtime/runtime.fbi $SOC_PREFIX
wget -P $SOC_PREFIX https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/master/bscan_spi_xc7k325t.bit

View File

@ -1,25 +0,0 @@
package:
name: artiq-kc705-nist_qc1
version: {{ environ.get("GIT_DESCRIBE_TAG", "") }}
source:
git_url: ../..
build:
noarch_python: true
number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
requirements:
build:
- migen 0.2
- misoc 0.2
- llvm-or1k
- binutils-or1k-linux
run:
- artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_DESCRIBE_HASH")[1:]) if "GIT_DESCRIBE_TAG" in environ else "" }}
about:
home: https://m-labs.hk/artiq
license: GPL
summary: 'Bitstream, BIOS and runtime for NIST_QC1 on the KC705 board'

View File

@ -8,16 +8,13 @@ source:
build:
noarch_python: true
number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:12] }}
requirements:
build:
- migen 0.2
- misoc 0.2
- llvm-or1k
- binutils-or1k-linux
- artiq-dev {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:12]) if "GIT_DESCRIBE_TAG" in environ else "" }}
run:
- artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_DESCRIBE_HASH")[1:]) if "GIT_DESCRIBE_TAG" in environ else "" }}
- artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:12]) if "GIT_DESCRIBE_TAG" in environ else "" }}
about:
home: https://m-labs.hk/artiq

View File

@ -8,16 +8,13 @@ source:
build:
noarch_python: true
number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:12] }}
requirements:
build:
- migen 0.2
- misoc 0.2
- llvm-or1k
- binutils-or1k-linux
- artiq-dev {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:12]) if "GIT_DESCRIBE_TAG" in environ else "" }}
run:
- artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_DESCRIBE_HASH")[1:]) if "GIT_DESCRIBE_TAG" in environ else "" }}
- artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:12]) if "GIT_DESCRIBE_TAG" in environ else "" }}
about:
home: http://m-labs.hk/artiq

View File

@ -8,34 +8,31 @@ source:
build:
noarch_python: true
number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:12] }}
requirements:
build:
- python >=3.5.2
- python 3.5.2
- setuptools
- numpy
- binutils-or1k-linux
run:
- python >=3.5.2
- python 3.5.2
- llvmlite-artiq 0.10.0.dev py35_24
- binutils-or1k-linux
- pythonparser 1.0
- openocd >=0.10
- lit
- outputcheck
- scipy
- numpy
- prettytable
- asyncserial
- sphinx
- sphinx-argparse
- h5py
- dateutil
- pyqt5
- pyqt >=5.5
- quamash
- pyqtgraph
- pyqtgraph 0.10.0
- pygit2
- aiohttp
- binutils-or1k-linux
- pythonparser
- levenshtein
test:

File diff suppressed because one or more lines are too long

File diff suppressed because one or more lines are too long

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@ -0,0 +1,14 @@
{% extends "!layout.html" %}
{# since sphinx_rtd_theme moves scripts to the end, hook up WaveDrom again #}
{%- block footer %}
{{ super() }}
<script>(function(){
window.addEventListener(
"load",
(function(){ try {
WaveDrom.ProcessAll();
} catch(e) {} }),
false);
})();</script>
{% endblock %}

View File

@ -10,9 +10,10 @@ A number of Python features can be used inside a kernel for compilation and exec
* Booleans
* 32-bit signed integers (default size)
* 64-bit signed integers (use ``int(n, width=64)`` to convert)
* 64-bit signed integers (use ``numpy.int64`` to convert)
* Double-precision floating point numbers
* Lists of any supported types
* String constants
* User-defined classes, with attributes of any supported types (attributes that are not used anywhere in the kernel are ignored)
For a demonstration of some of these features, see the ``mandelbrot.py`` example.
@ -29,23 +30,50 @@ Kernel code can call host functions without any additional ceremony. However, su
The Python types correspond to ARTIQ type annotations as follows:
+-------------+-------------------------+
| Python | ARTIQ |
+=============+=========================+
| NoneType | TNone |
+-------------+-------------------------+
| bool | TBool |
+-------------+-------------------------+
| int | TInt32, TInt64 |
+-------------+-------------------------+
| float | TFloat |
+-------------+-------------------------+
| str | TStr |
+-------------+-------------------------+
| list of T | TList(T) |
+-------------+-------------------------+
| range | TRange32, TRange64 |
+-------------+-------------------------+
+---------------+-------------------------+
| Python | ARTIQ |
+===============+=========================+
| NoneType | TNone |
+-------------+---------------------------+
| bool | TBool |
+-------------+---------------------------+
| int | TInt32 or TInt64 |
+-------------+---------------------------+
| float | TFloat |
+-------------+---------------------------+
| str | TStr |
+-------------+---------------------------+
| list of T | TList(T) |
+-------------+---------------------------+
| range | TRange32, TRange64 |
+-------------+---------------------------+
| numpy.int32 | TInt32 |
+-------------+---------------------------+
| numpy.int64 | TInt64 |
+-------------+---------------------------+
| numpy.float64 | TFloat |
+-------------+---------------------------+
Pitfalls
--------
The ARTIQ compiler accepts *nearly* a strict subset of Python 3. However, by necessity there
is a number of differences that can lead to bugs.
Arbitrary-length integers are not supported at all on the core device; all integers are
either 32-bit or 64-bit. This especially affects calculations that result in a 32-bit signed
overflow; if the compiler detects a constant that doesn't fit into 32 bits, the entire expression
will be upgraded to 64-bit arithmetics, however if all constants are small, 32-bit arithmetics
will be used even if the result will overflow. Overflows are not detected.
The result of calling the builtin ``round`` function is different when used with
the builtin ``float`` type and the ``numpy.float64`` type on the host interpreter; ``round(1.0)``
returns an integer value 1, whereas ``round(numpy.float64(1.0))`` returns a floating point value
``numpy.float64(1.0)``. Since both ``float`` and ``numpy.float64`` are mapped to
the builtin ``float`` type on the core device, this can lead to problems in functions marked
``@portable``; the workaround is to explicitly cast the argument of ``round`` to ``float``:
``round(float(numpy.float64(1.0)))`` returns an integer on the core device as well as on the host
interpreter.
Additional optimizations
------------------------

View File

@ -16,6 +16,7 @@
import sys
import os
import sphinx_rtd_theme
from unittest.mock import MagicMock
@ -27,7 +28,13 @@ class Mock(MagicMock):
return Mock()
mock_modules = ["artiq.gui.moninj", "quamash", "pyqtgraph", "matplotlib"]
mock_modules = ["artiq.gui.moninj",
"artiq.gui.waitingspinnerwidget",
"artiq.gui.flowlayout",
"quamash", "pyqtgraph", "matplotlib",
"numpy", "dateutil", "dateutil.parser", "prettytable", "PyQt5",
"h5py", "serial", "scipy", "scipy.interpolate", "asyncserial",
"llvmlite_artiq", "Levenshtein", "aiohttp"]
for module in mock_modules:
sys.modules[module] = Mock()
@ -36,7 +43,7 @@ for module in mock_modules:
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
sys.path.insert(0, os.path.abspath('..'))
sys.path.insert(0, os.path.abspath('../..'))
from artiq import __version__ as artiq_version
@ -52,7 +59,9 @@ extensions = [
'sphinx.ext.autodoc',
'sphinx.ext.mathjax',
'sphinx.ext.viewcode',
'sphinx.ext.napoleon',
'sphinxarg.ext',
'sphinxcontrib.wavedrom', # see also below for config
]
# Add any paths that contain templates here, relative to this directory.
@ -69,7 +78,7 @@ master_doc = 'index'
# General information about the project.
project = 'ARTIQ'
copyright = '2014-2016, M-Labs Limited'
copyright = '2014-2017, M-Labs Limited'
# The version info for the project you're documenting, acts as replacement for
# |version| and |release|, also used in various other places throughout the
@ -123,24 +132,16 @@ pygments_style = 'sphinx'
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
html_theme = 'classic'
html_theme = 'sphinx_rtd_theme'
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the
# documentation.
html_theme_options = {
'sidebarbgcolor': '#171814',
'sidebarlinkcolor': '#7389ae',
'sidebartextcolor': '#b3b3bb',
'footerbgcolor': '#171814',
'footertextcolor': '#b3b3bb',
'relbarbgcolor': '#171814',
'relbarlinkcolor': '#7389ae',
'relbartextcolor': '#b3b3bb',
}
html_theme_options = {}
# Add any paths that contain custom themes here, relative to this directory.
#html_theme_path = []
html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
# The name for this set of Sphinx documents. If None, it defaults to
# "<project> v<release> documentation".
@ -151,7 +152,7 @@ html_theme_options = {
# The name of an image file (relative to this directory) to place at the top
# of the sidebar.
html_logo = "../logo/artiq_white.png"
html_logo = '../logo/artiq_white.png'
# The name of an image file (within the static path) to use as favicon of the
# docs. This file should be a Windows icon file (.ico) being 16x16 or 32x32
@ -290,3 +291,7 @@ texinfo_documents = [
# If true, do not generate a @detailmenu in the "Top" node's menu.
#texinfo_no_detailmenu = False
# -- Options for sphinxcontrib-wavedrom -----------------------------------
offline_skin_js_path = '_static/default.js'
offline_wavedrom_js_path = '_static/WaveDrom.js'

View File

@ -38,6 +38,12 @@ Common problems
* When connected, QC1 and CLOCK adapters break the JTAG chain due to TDI not being connect to TDO on the FMC mezzanine.
* On some boards, the JTAG USB connector is not correctly soldered.
VADJ
++++
With the NIST CLOCK and QC2 adapters, for safe operation of the DDS buses (to prevent damage to the IO banks of the FPGA), the FMC VADJ rail of the KC705 should be changed to 3.3V. Plug the Texas Instruments USB-TO-GPIO PMBus adapter into the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software to configure (requires Windows). Write to chip number U55 (address 52), channel 4, which is the VADJ rail, to make it 3.3V instead of 2.5V. Power cycle the KC705 board to check that the startup voltage on the VADJ rail is now 3.3V.
NIST QC1
++++++++
@ -149,8 +155,6 @@ To avoid I/O contention, the startup kernel should first program the TCA6424A ex
See :mod:`artiq.coredevice.i2c` for more details.
For safe operation of the DDS buses (to prevent damage to the IO banks of the FPGA), the FMC VADJ rail of the KC705 should be changed to 3.3V. Plug the Texas Instruments USB-TO-GPIO PMBus adapter into the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software to configure (requires Windows). Write to chip number U55 (address 52), channel 4, which is the VADJ rail, to make it 3.3V instead of 2.5V. Power cycle the KC705 board to check that the startup voltage on the VADJ rail is now 3.3V.
Pipistrello
-----------

View File

@ -21,15 +21,9 @@ As a very first step, we will turn on a LED on the core device. Create a file ``
self.core.reset()
self.led.on()
The central part of our code is our ``LED`` class, that derives from :class:`artiq.language.environment.EnvExperiment`. Among other features, ``EnvExperiment`` calls our ``build`` method and provides the ``setattr_device`` method that interfaces to the device database to create the appropriate device drivers and make those drivers accessible as ``self.core`` and ``self.led``. The ``@kernel`` decorator tells the system that the ``run`` method must be executed on the core device (instead of the host). The decorator uses ``self.core`` internally, which is why we request the core device using ``setattr_device`` like any other.
The central part of our code is our ``LED`` class, that derives from :class:`artiq.language.environment.EnvExperiment`. Among other features, ``EnvExperiment`` calls our ``build`` method and provides the ``setattr_device`` method that interfaces to the device database to create the appropriate device drivers and make those drivers accessible as ``self.core`` and ``self.led``. The ``@kernel`` decorator tells the system that the ``run`` method must be compiled for and executed on the core device (instead of being interpreted and executed as regular Python code on the host). The decorator uses ``self.core`` internally, which is why we request the core device using ``setattr_device`` like any other.
Copy the file ``device_db.pyon`` (containing the device database) from the ``examples/master`` folder of ARTIQ into the same directory as ``led.py`` (alternatively, you can use the ``--device-db`` option of ``artiq_run``). You can open PYON database files using a text editor - their contents are in a human-readable format. You will probably want to set the IP address of the core device in ``device_db.pyon`` so that the computer can connect to it (it is the ``host`` parameter of the ``comm`` entry). See :ref:`device-db` for more information. The example device database is designed for the NIST QC1 hardware on the KC705; see :ref:`board-ports` for RTIO channel assignments if you need to adapt the device database to a different hardware platform.
.. note::
If the ``led`` device is a bidirectional TTL (i.e. ``TTLInOut`` instead of ``TTLOut``), you need to put it in output (driving) mode. Add the following at the beginning of ``run``: ::
self.led.output()
delay(0.1*us)
Copy the file ``device_db.pyon`` (containing the device database) from the ``examples/master`` folder of ARTIQ into the same directory as ``led.py`` (alternatively, you can use the ``--device-db`` option of ``artiq_run``). You can open PYON database files using a text editor - their contents are in a human-readable format. You will probably want to set the IP address of the core device in ``device_db.pyon`` so that the computer can connect to it (it is the ``host`` parameter of the ``comm`` entry). See :ref:`device-db` for more information. The example device database is designed for the ``nist_clock`` hardware adapter on the KC705; see :ref:`board-ports` for RTIO channel assignments if you need to adapt the device database to a different hardware platform.
.. note::
To obtain the examples, you can find where the ARTIQ package is installed on your machine with: ::
@ -42,8 +36,8 @@ Run your code using ``artiq_run``, which is part of the ARTIQ front-end tools: :
The process should terminate quietly and the LED of the device should turn on. Congratulations! You have a basic ARTIQ system up and running.
Host/core device interaction
----------------------------
Host/core device interaction (RPC)
----------------------------------
A method or function running on the core device (which we call a "kernel") may communicate with the host by calling non-kernel functions that may accept parameters and may return a value. The "remote procedure call" (RPC) mechanisms handle automatically the communication between the host and the device of which function to call, with which parameters, and what the returned value is.
@ -77,12 +71,16 @@ You can then turn the LED off and on by entering 0 or 1 at the prompt that appea
What happens is the ARTIQ compiler notices that the ``input_led_state`` function does not have a ``@kernel`` decorator and thus must be executed on the host. When the core device calls it, it sends a request to the host to execute it. The host displays the prompt, collects user input, and sends the result back to the core device, which sets the LED state accordingly.
RPC functions must always return a value of the same type. When they return a non-``None`` value, the compiler should be informed in advance of the type of the value, which is what the ``-> TBool`` annotation is for.
RPC functions must always return a value of the same type. When they return a value that is not ``None``, the compiler should be informed in advance of the type of the value, which is what the ``-> TBool`` annotation is for.
The ``break_realtime`` call is necessary to waive the real-time requirements of the LED state change (as the ``input_led_state`` function can take an arbitrarily long time). This will become clearer later as we explain timing control.
Without the ``break_realtime()`` call, the RTIO events emitted by ``self.led.on()`` or ``self.led.off()`` would be scheduled at a fixed and very short delay after entering ``run()``.
These events would fail because the RPC to ``input_led_state()`` can take an arbitrary amount of time and therefore the deadline for submission of RTIO events would have long passed when ``self.led.on()`` or ``self.led.off()`` are called.
The ``break_realtime()`` call is necessary to waive the real-time requirements of the LED state change.
It advances the timeline far enough to ensure that events can meet the submission deadline.
Real-time I/O
-------------
Real-time I/O (RTIO)
--------------------
The point of running code on the core device is the ability to meet demanding real-time constraints. In particular, the core device can respond to an incoming stimulus or the result of a measurement with a low and predictable latency. We will see how to use inputs later; first, we must familiarize ourselves with how time is managed in kernels.
@ -99,18 +97,28 @@ Create a new file ``rtio.py`` containing the following: ::
@kernel
def run(self):
self.core.reset()
self.ttl0.output()
for i in range(1000000):
self.ttl0.pulse(2*us)
delay(2*us)
self.ttl0.pulse(2*us)
In its ``build()`` method, the experiment obtains the core device and a TTL device called ``ttl0`` as defined in the device database.
In ARTIQ, TTL is used roughly synonymous with "a single generic digital signal" and does not refer to a specific signaling standard or voltage/current levels.
.. note::
If ``ttl0`` is a bidirectional channel (``TTLInOut``), it is in input (non-driving) mode by default. You need to call ``self.ttl0.output()`` as explained above for the LED.
When ``run()``, the experiment first ensures that ``ttl0`` is in output mode and actively driving the device it is connected to.
Bidirectional TTL channels (i.e. ``TTLInOut``) are in input (high impedance) mode by default, output-only TTL channels (``TTLOut``) are always in output mode.
There are no input-only TTL channels.
The experiment then drives one million 2 µs long pulses separated by 2 µs each.
Connect an oscilloscope or logic analyzer to TTL0 and run ``artiq_run.py rtio.py``.
Notice that the generated signal's period is precisely 4 µs, and that it has a duty cycle of precisely 50%.
This is not what you would expect if the delay and the pulse were implemented with register-based general purpose input output (GPIO) that is CPU-controlled.
The signal's period would depend on CPU speed, and overhead from the loop, memory management, function calls, etc, all of which are hard to predict and variable.
Any asymmetry in the overhead would manifest itself in a distorted and variable duty cycle.
Connect an oscilloscope or logic analyzer to TTL0 and run ``artiq_run.py led.py``. Notice that the generated signal's period is precisely 4 microseconds, and that it has a duty cycle of precisely 50%. This is not what you would expect if the delay and the pulse were implemented with CPU-controlled GPIO: overhead from the loop management, function calls, etc. would increase the signal's period, and asymmetry in the overhead would cause duty cycle distortion.
Instead, inside the core device, output timing is generated by the gateware and the CPU only programs switching commands with certain timestamps that the CPU computes.
Instead, inside the core device, output timing is generated by the gateware and the CPU only programs switching commands with certain timestamps that the CPU computes. This guarantees precise timing as long as the CPU can keep generating timestamps that are increasing fast enough. In case it fails to do that (and attempts to program an event with a timestamp in the past), the :class:`artiq.coredevice.exceptions.RTIOUnderflow` exception is raised. The kernel causing it may catch it (using a regular ``try... except...`` construct), or it will be propagated to the host.
This guarantees precise timing as long as the CPU can keep generating timestamps that are increasing fast enough. In case it fails to do that (and attempts to program an event with a timestamp smaller than the current RTIO clock timestamp), a :class:`artiq.coredevice.exceptions.RTIOUnderflow` exception is raised. The kernel causing it may catch it (using a regular ``try... except...`` construct), or it will be propagated to the host.
Try reducing the period of the generated waveform until the CPU cannot keep up with the generation of switching events and the underflow exception is raised. Then try catching it: ::
@ -135,6 +143,38 @@ Try reducing the period of the generated waveform until the CPU cannot keep up w
except RTIOUnderflow:
print_underflow()
Parallel and sequential blocks
------------------------------
It is often necessary that several pulses overlap one another. This can be expressed through the use of ``with parallel`` constructs, in which the events generated by the individual statements are executed at the same time. The duration of the ``parallel`` block is the duration of its longest statement.
Try the following code and observe the generated pulses on a 2-channel oscilloscope or logic analyzer: ::
for i in range(1000000):
with parallel:
self.ttl0.pulse(2*us)
self.ttl1.pulse(4*us)
delay(4*us)
ARTIQ can implement ``with parallel`` blocks without having to resort to any of the typical parallel processing approaches.
It simply remembers the position on the timeline when entering the ``parallel`` block and then seeks back to that position after submitting the events generated by each statement.
In other words, the statements in the ``parallel`` block are actually executed sequentially, only the RTIO events generated by them are scheduled to be executed in parallel.
Note that if a statement takes a lot of CPU time to execute (this different from the events scheduled by a statement taking a long time), it may cause a subsequent statement to miss the deadline for timely submission of its events.
This then causes a ``RTIOUnderflow`` exception to be raised.
Within a parallel block, some statements can be made sequential again using a ``with sequential`` construct. Observe the pulses generated by this code: ::
for i in range(1000000):
with parallel:
with sequential:
self.ttl0.pulse(2*us)
delay(1*us)
self.ttl0.pulse(1*us)
self.ttl1.pulse(4*us)
delay(4*us)
RTIO analyzer
-------------
@ -157,30 +197,3 @@ The core device records the real-time I/O waveforms into a circular buffer. It i
delay(...)
Afterwards, the recorded data can be extracted and written to a VCD file using ``artiq_coreanalyzer -w rtio.vcd`` (see: :ref:`core-device-rtio-analyzer-tool`). VCD files can be viewed using third-party tools such as GtkWave.
Parallel and sequential blocks
------------------------------
It is often necessary that several pulses overlap one another. This can be expressed through the use of ``with parallel`` constructs, in which all statements execute at the same time. The execution time of the ``parallel`` block is the execution time of its longest statement.
Try the following code and observe the generated pulses on a 2-channel oscilloscope or logic analyzer: ::
for i in range(1000000):
with parallel:
self.ttl0.pulse(2*us)
self.ttl1.pulse(4*us)
delay(4*us)
Within a parallel block, some statements can be made sequential again using a ``with sequential`` construct. Observe the pulses generated by this code: ::
for i in range(1000000):
with parallel:
with sequential:
self.ttl0.pulse(2*us)
delay(1*us)
self.ttl0.pulse(1*us)
self.ttl1.pulse(4*us)
delay(4*us)
.. note::
Branches of a ``parallel`` block are executed one after another, with a reset of the internal RTIO time variable before moving to the next branch. If a branch takes a lot of CPU time, it may cause an underflow when the next branch begins its execution.

View File

@ -10,6 +10,7 @@ Contents:
installing
installing_from_source
release_notes
rtio
getting_started_core
compiler
getting_started_mgmt

View File

@ -31,7 +31,11 @@ Executing just ``conda`` should print the help of the ``conda`` command [1]_.
Installing the ARTIQ packages
-----------------------------
Add the M-Labs ``main`` Anaconda package repository containing stable releases and release candidates to your conda configuration::
First add the conda-forge repository containing ARTIQ dependencies to your conda configuration::
$ conda config --add channels http://conda.anaconda.org/conda-forge/label/main
Then add the M-Labs ``main`` Anaconda package repository containing stable releases and release candidates::
$ conda config --add channels http://conda.anaconda.org/m-labs/label/main

View File

@ -43,10 +43,9 @@ and the ARTIQ kernels.
* Install LLVM and Clang: ::
$ cd ~/artiq-dev
$ git clone https://github.com/openrisc/llvm-or1k
$ cd llvm-or1k/tools
$ git clone https://github.com/openrisc/clang-or1k clang
$ cd ..
$ git clone -b artiq-3.8 https://github.com/m-labs/llvm-or1k
$ cd llvm-or1k
$ git clone -b artiq-3.8 https://github.com/m-labs/clang-or1k tools/clang
$ mkdir build
$ cd build
@ -146,7 +145,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
$ python3.5 -m artiq.gateware.targets.kc705 -H nist_qc1 # or nist_qc2
.. note:: Add ``--toolchain vivado`` if you wish to use Vivado instead of ISE.
.. note:: Add ``--toolchain ise`` if you wish to use ISE instead of Vivado.
* Then, gather the binaries and flash them: ::

View File

@ -31,4 +31,4 @@ Website: https://m-labs.hk/artiq
`Cite ARTIQ <http://dx.doi.org/10.5281/zenodo.51303>`_ as ``Bourdeauducq, Sébastien et al. (2016). ARTIQ 1.0. Zenodo. 10.5281/zenodo.51303``.
Copyright (C) 2014-2016 M-Labs Limited. Licensed under GNU GPL version 3.
Copyright (C) 2014-2017 M-Labs Limited. Licensed under GNU GPL version 3.

View File

@ -72,7 +72,9 @@ To check whether ``pause()`` would in fact *not* return immediately, use :meth:`
The experiment must place the hardware in a safe state and disconnect from the core device (typically, by using ``self.core.comm.close()``) before calling ``pause``.
Accessing the ``pause`` method is done through a virtual device called ``scheduler`` that is accessible to all experiments. The scheduler virtual device is requested like regular devices using ``get_device`` or ``attr_device``.
Accessing the ``pause`` and ``check_pause`` methods is done through a virtual device called ``scheduler`` that is accessible to all experiments. The scheduler virtual device is requested like regular devices using ``get_device`` or ``attr_device``.
``check_pause`` can be called (via RPC) from a kernel, but ``pause`` must not.
Multiple pipelines
------------------

228
doc/manual/rtio.rst Normal file
View File

@ -0,0 +1,228 @@
ARTIQ Real-Time I/O Concepts
============================
The ARTIQ Real-Time I/O design employs several concepts to achieve its goals of high timing resolution on the nanosecond scale and low latency on the microsecond scale while still not sacrificing a readable and extensible language.
In a typical environment two very different classes of hardware need to be controlled.
One class is the vast arsenal of diverse laboratory hardware that interfaces with and is controlled from a typical PC.
The other is specialized real-time hardware
that requires tight coupling and a low-latency interface to a CPU.
The ARTIQ code that describes a given experiment is composed of two types of "programs":
regular Python code that is executed on the host and ARTIQ *kernels* that are executed on a *core device*.
The CPU that executes the ARTIQ kernels has direct access to specialized programmable I/O timing logic (part of the *gateware*).
The two types of code can invoke each other and transitions between them are seamless.
The ARTIQ kernels do not interface with the real-time gateware directly.
That would lead to imprecise, indeterminate, and generally unpredictable timing.
Instead the CPU operates at one end of a bank of FIFO (first-in-first-out) buffers while the real-time gateware at the other end guarantees the *all or nothing* level of excellent timing precision.
A FIFO for an output channel hold timestamps and event data describing when and what is to be executed.
The CPU feeds events into this FIFO.
A FIFO for an input channel contains timestamps and event data for events that have been recorded by the real-time gateware and are waiting to be read out by
the CPU on the other end.
The timeline
------------
The set of all input and output events on all channels constitutes the *timeline*.
A high resolution wall clock (``rtio_counter``) counts clock cycles and causes output events to be executed when their timestamp matches the clock and input events to be recorded and stamped with the current clock value accordingly.
The kernel runtime environment maintains a timeline cursor (called ``now``) used as the timestamp when output events are submitted to the FIFOs.
This timeline cursor can be moved forward or backward on the timeline relative to its current value using :func:`artiq.language.core.delay` and :func:`artiq.language.core.delay_mu`, the later being a delay given in *machine units* as opposed to SI units.
The absolute value of ``now`` on the timeline can be retrieved using :func:`artiq.language.core.now_mu` and it can be set using :func:`artiq.language.core.at_mu`.
RTIO timestamps, the timeline cursor, and the ``rtio_counter`` wall clock are all relative to the core device startup/boot time.
The wall clock keeps running across experiments.
Absolute timestamps can be large numbers.
They are represented internally as 64-bit integers with a resolution of typically a nanosecond and a range of hundreds of years.
Conversions between such a large integer number and a floating point representation can cause loss of precision through cancellation.
When computing the difference of absolute timestamps, use ``mu_to_seconds(t2-t1)``, not ``mu_to_seconds(t2)-mu_to_seconds(t1)`` (see :meth:`artiq.language.core.mu_to_seconds`).
When accumulating time, do it in machine units and not in SI units, so that rounding errors do not accumulate.
The following basic example shows how to place output events on the timeline.
It emits a precisely timed 2 µs pulse::
ttl.on()
delay(2*us)
ttl.off()
The device ``ttl`` represents a single digital output channel
(:class:`artiq.coredevice.ttl.TTLOut`).
The :meth:`artiq.coredevice.ttl.TTLOut.on` method places an rising edge on the timeline at the current cursor position (``now``).
Then the cursor is moved forward 2 µs and a falling edge event is placed at the new cursor position.
Then later, when the wall clock reaches the respective timestamps the RTIO gateware executes the two events.
The following diagram shows what is going on at the different levels of the software and gateware stack (assuming one machine unit of time is 1 ns):
.. wavedrom::
{
signal: [
{name: 'kernel', wave: 'x32.3x', data: ['on()', 'delay(2*us)', 'off()'], node: '..A.XB'},
{name: 'now', wave: '2...2.', data: ['7000', '9000'], node: '..P..Q'},
{},
{name: 'slack', wave: 'x2x.2x', data: ['4400', '5800']},
{},
{name: 'rtio_counter', wave: 'x2x|2x|2x2x', data: ['2600', '3200', '7000', '9000'], node: ' V.W'},
{name: 'ttl', wave: 'x1.0', node: ' R.S', phase: -6.5},
{ node: ' T.U', phase: -6.5}
],
edge: [
'A~>R', 'P~>R', 'V~>R', 'B~>S', 'Q~>S', 'W~>S',
'R-T', 'S-U', 'T<->U 2µs'
],
}
The sequence is exactly equivalent to::
ttl.pulse(2*us)
The :meth:`artiq.coredevice.ttl.TTLOut.pulse` method advances the timeline cursor (using ``delay()``) while other methods such as :meth:`artiq.coredevice.ttl.TTLOut.on`, :meth:`artiq.coredevice.ttl.TTLOut.off`, :meth:`artiq.coredevice.dds._DDSGeneric.set`, or the ``set_*()`` methods of :class:`artiq.coredevice.spi.SPIMaster` do not. The latter are called *zero-duration* methods.
Underflow exceptions
--------------------
An RTIO event must always be programmed with a timestamp in the future.
In other words, the timeline cursor ``now`` must be after the current wall clock ``rtio_counter``: the past can not be altered.
The following example tries to place an rising edge event on the timeline.
If the current cursor is in the past, an :class:`artiq.coredevice.exceptions.RTIOUnderflow` exception is thrown.
The experiment attempts to handle the exception by moving the cursor forward and repeating the programming of the rising edge::
try:
ttl.on()
except RTIOUnderflow:
# try again at the next mains cycle
delay(16.6667*ms)
ttl.on()
.. wavedrom::
{
signal: [
{name: 'kernel', wave: 'x34..2.3x', data: ['on()', 'RTIOUnderflow', 'delay()', 'on()'], node: '..AB....C', phase: -3},
{name: 'now_mu', wave: '2.....2', data: ['t0', 't1'], node: '.D.....E', phase: -4},
{},
{name: 'slack', wave: '2x....2', data: ['< 0', '> 0'], node: '.T', phase: -4},
{},
{name: 'rtio_counter', wave: 'x2x.2x....2x2', data: ['t0', '> t0', '< t1', 't1'], node: '............P'},
{name: 'tll', wave: 'x...........1', node: '.R..........S', phase: -.5}
],
edge: [
'A-~>R forbidden', 'D-~>R', 'T-~B exception',
'C~>S allowed', 'E~>S', 'P~>S'
]
}
To track down ``RTIOUnderflows`` in an experiment there are a few approaches:
* Exception backtraces show where underflow has occurred while executing the
code.
* The :any:`integrated logic analyzer <core-device-rtio-analyzer-tool>` shows the timeline context that lead to the exception. The analyzer is always active and supports plotting of RTIO slack. RTIO slack is the difference between timeline cursor and wall clock time (``now - rtio_counter``).
Input channels and events
-------------------------
Input channels detect events, timestamp them, and place them in a buffer for the experiment to read out.
The following example counts the rising edges occurring during a precisely timed 500 ns interval.
If more than 20 rising edges were received it outputs a pulse::
input.gate_rising(500*ns)
if input.count() > 20:
delay(2*us)
output.pulse(500*ns)
The :meth:`artiq.coredevice.ttl.TTLInOut.count` method of an input channel can lead to a situation of negative slack (timeline cursor ``now`` smaller than the current wall clock ``rtio_counter``):
The :meth:`artiq.coredevice.ttl.TTLInOut.gate_rising` method leaves the timeline cursor at the closure time of the gate and ``count()`` must necessarily wait until the gate closing event has actually been executed which is sometime with ``rtio_counter > now``.
In these situations where ``count()`` leads to a synchronization of timeline cursor and wall clock, a ``delay()`` is necessary to reestablish positive slack so that output events can be placed.
.. wavedrom::
{
signal: [
{name: 'kernel', wave: '3..5.|2.3..x..', data: ['gate_rising()', 'count()', 'delay()', 'pulse()'], node: '.A.B..C.ZD.E'},
{name: 'now_mu', wave: '2.2..|..2.2.', node: '.P.Q....XV.W'},
{},
{},
{name: 'input gate', wave: 'x1.0', node: '.T.U', phase: -2.5},
{name: 'output', wave: 'x1.0', node: '.R.S', phase: -10.5}
],
edge: [
'A~>T', 'P~>T', 'B~>U', 'Q~>U', 'U~>C', 'D~>R', 'E~>S', 'V~>R', 'W~>S'
]
}
Overflow exceptions
-------------------
The RTIO input channels buffer input events received while an input gate is open.
The events are kept in a FIFO until the CPU reads them out via ``count()`` (or :meth:`artiq.coredevice.ttl.TTLInOut.timestamp_mu`).
If the FIFO is full and another event is coming in, this causes an overflow condition.
The condition is converted into an :class:`artiq.coredevice.exceptions.RTIOOverflow` exception that is raised on a subsequent invocation of one of the readout methods (``count()`` or ``timestamp_mu()``).
Seamless handover
-----------------
The timeline cursor persists across kernel invocations.
This is demonstrated in the following example where a pulse is split across two kernels::
def run():
k1()
k2()
@kernel
def k1():
ttl.on()
delay(1*s)
@kernel
def k2():
ttl.off()
Here, ``run()`` calls ``k1()`` which exits leaving the cursor one second after the rising edge and ``k2()`` then submits a falling edge at that position.
.. wavedrom::
{
signal: [
{name: 'kernel', wave: '3.2..2..|3.', data: ['k1: on()', 'k1: delay(dt)', 'k1->k2 swap', 'k2: off()'], node: '..A........B'},
{name: 'now', wave: '2....2...|.', data: ['t', 't+dt'], node: '..P........Q'},
{},
{},
{name: 'rtio_counter', wave: 'x......|2xx|2', data: ['t', 't+dt'], node: '........V...W'},
{name: 'ttl', wave: 'x1...0', node: '.R...S', phase: -7.5},
{ node: ' T...U', phase: -7.5}
],
edge: [
'A~>R', 'P~>R', 'V~>R', 'B~>S', 'Q~>S', 'W~>S',
'R-T', 'S-U', 'T<->U dt'
],
}
Synchronization
---------------
The seamless handover of the timeline (cursor and events) across kernels and experiments implies that a kernel can exit long before the events it has submitted have been executed.
If a previous kernel sets timeline cursor far in the future this effectively locks the system.
When a kernel should wait until all the events on a particular channel have been executed, use the :meth:`artiq.coredevice.ttl.TTLOut.sync` method of a channel:
.. wavedrom::
{
signal: [
{name: 'kernel', wave: 'x3x.|5.|x', data: ['on()', 'sync()'], node: '..A.....Y'},
{name: 'now', wave: '2..', data: ['7000'], node: '..P'},
{},
{},
{name: 'rtio_counter', wave: 'x2x.|..2x', data: ['2000', '7000'], node: ' ....V'},
{name: 'ttl', wave: 'x1', node: ' R', phase: -6.5},
],
edge: [
'A~>R', 'P~>R', 'V~>R', 'V~>Y'
],
}
RTIO reset
-----------
The seamless handover also means that a kernel is not guaranteed to always be executed with positive slack.
An experiment can face any of these circumstances (large positive slack, full FIFOs, or negative slack).
Therefore, when switching experiments it can be adequate to clear the RTIO FIFOs and initialize the timeline cursor to "sometime in the near future" using :meth:`artiq.coredevice.core.Core.reset`.
The example idle kernel implements this mechanism.
Since it never waits for any input, it will rapidly fill the output FIFOs and would produce a large positive slack.
To avoid large positive slack and to accommodate for seamless handover the idle kernel will only run when no other experiment is pending and the example will wait before submitting events until there is significant negative slack.

View File

@ -12,7 +12,8 @@ if sys.version_info[:3] < (3, 5, 2):
# Depends on PyQt5, but setuptools cannot check for it.
requirements = [
"sphinx", "sphinx-argparse", "asyncserial", "numpy", "scipy",
"sphinx", "sphinx-argparse", "sphinxcontrib-wavedrom", "sphinx_rtd_theme",
"asyncserial", "numpy", "scipy",
"python-dateutil", "prettytable", "h5py",
"quamash", "pyqtgraph", "pygit2", "aiohttp",
"llvmlite_artiq", "pythonparser", "python-Levenshtein",
@ -59,7 +60,7 @@ Development Status :: 5 - Production/Stable
Environment :: Console
Environment :: X11 Applications :: Qt
Intended Audience :: Science/Research
License :: OSI Approved :: GNU General Public License v3 or later (GPLv3+)
License :: OSI Approved :: GNU Lesser General Public License v3 or later (LGPLv3+)
Operating System :: Microsoft :: Windows
Operating System :: POSIX :: Linux
Programming Language :: Python :: 3.5