M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity
8,880 Commits 13 Branches 35 Tags 25 MiB
Commit Graph

8880 Commits

Author SHA1 Message Date
occheung 790a20edf6 linker: generate stack guard + symbol 2021-10-16 17:42:24 +08:00
fanmingyu212 178a86bcda master: add an argument to set an experiment subdirectory 
Signed-off-by: Mingyu Fan <mingyufan@ucsb.edu>
 2021-10-15 16:54:31 +08:00
Sebastien Bourdeauducq 35d21c98d3 Revert "runtime: expose rint from libm" 
Consistency with NAR3/Zynq where rint is not available.

This reverts commit f5100702f6.
 2021-10-11 08:12:04 +08:00
Sebastien Bourdeauducq f5100702f6 runtime: expose rint from libm 2021-10-10 20:40:17 +08:00
Sebastien Bourdeauducq 3c1cbf47d2 phaser: add more slack during init. Closes #1757 2021-10-10 16:18:55 +08:00
Robert Jördens 3f6bf33298 fastino: add interpolator support 2021-10-08 15:47:07 +00:00
Harry Ho 501eb1fa23 flake: add microscope 2021-10-08 12:39:35 +08:00
Harry Ho ea9bc04407 flake: add jesd204b 2021-10-08 12:39:35 +08:00
occheung 59065c4663 alloc_list: support alloc w/ large align 
Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
 2021-10-07 12:38:03 +08:00
Spaqin 1894f0f626
gateware: share RTIOClockMultiplier and fix_serdes_timing_path (#1760) 2021-10-07 08:19:38 +08:00
Sebastien Bourdeauducq 4bfd010f03 setup: Python 3.7+ 2021-09-27 17:46:25 +08:00
Etienne Wodey a8333053c9 sinara_tester: add device_db and test selection CLI options 
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
 2021-09-27 17:44:50 +08:00
occheung 7a7e17f7e3 openocd: update and apply 4-byte address support patch 
See the relevant commit made in nix-scripts repo.
575ef05cd5
 2021-09-27 09:34:46 +08:00
Sebastien Bourdeauducq 3ed10221d8 compiler: remove big-endian support. Closes #1590 2021-09-13 13:40:24 +08:00
Sebastien Bourdeauducq e8a7a8f41e compiler: work around idiotic windoze behavior that causes conda ld.lld not to be found 2021-09-13 10:40:54 +08:00
Sebastien Bourdeauducq 4834966798 flake: add jsonschema to dev environment 2021-09-13 07:39:15 +08:00
Sebastien Bourdeauducq 7209e6f279 flake: add cargo-xbuild to dev environment 2021-09-13 07:20:36 +08:00
Sebastien Bourdeauducq ffb1e3ec2d wavesynth: np.int is deprecated 2021-09-13 07:02:35 +08:00
Sebastien Bourdeauducq 2d79d824f9 firmware: remove minor or1k leftovers 2021-09-12 20:03:37 +08:00
Sebastien Bourdeauducq 1a0c4219ec doc: mor1kx -> VexRiscv 2021-09-12 19:27:00 +08:00
Sebastien Bourdeauducq 2e5c32878f flake: add other KC705 NIST builds 2021-09-10 17:19:32 +08:00
occheung a573dcf3f9 board_misoc/build: use rv32 as target arg 
The original rv64 argument was only to match the misoc counterpart.
 2021-09-10 14:11:23 +08:00
occheung 448974fe11 runtime/main: cleanup 2021-09-10 13:59:53 +08:00
occheung b091d8cb66 kernel: flush cache before mod_init 
This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq d50e24acb1 update dependencies 2021-09-10 13:25:12 +08:00
occheung 5394d04669 test_spi: add delay 2021-09-10 13:25:12 +08:00
occheung b8ed5a0d91 alloc: fix alignment for riscv32 arch 2021-09-10 13:25:12 +08:00
occheung 2213e7ffac ksupp/rtio/exception: fix timestamp 2021-09-10 13:25:12 +08:00
occheung 09ffd9de1e dma: fix timestamp fetch 2021-09-10 13:25:12 +08:00
occheung 051a14abf2 rtio/dma: fix endianness 2021-09-10 13:25:12 +08:00
occheung c6ba0f3cf4 ksupport: fix dma cslice (ffi) 2021-09-10 13:25:12 +08:00
occheung c812a837ab runtime: enlarge stack size 2021-09-10 13:25:12 +08:00
occheung a596db404d satman: fix cargo xbuild sysroot 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq eff7ae5aff flake: make llvm-strip in HITL test 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq c78fbe9bd2 flake: make bscanspi bitstreams available in HITL test 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 17b9d2fc5a flake: add KC705 HITL test 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 5e2664ae7e flake: add openocd 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 64ce7e498b flake: make board package a Python package 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 952acce65b flake: build board package on Hydra 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 7ae4b2d9bb flake: update dependencies 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq ce0964e25f flake: fix cargo sha256 2021-09-10 13:25:12 +08:00
occheung 4fab267593 cargo: std dependency hack 2021-09-10 13:25:12 +08:00
occheung dcbd9f905c cargo: use cargo xbuild 2021-09-10 13:25:12 +08:00
occheung 9f6b3f6014 firmware: clarify target triple 
The lack of compressed instruction support can be inferred from the target triple, literally.
 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 9697ec33eb flake: update dependencies 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq eee80c7697 flake: use improved Rust support in nixpkgs 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq b7efb2f633 flake: remove outdated comment 2021-09-10 13:25:12 +08:00
Sebastien Bourdeauducq 9ee03bd438 flake: reenable lit test 2021-09-10 13:25:12 +08:00
occheung 4619a33db4 test: remove broken array return tests 
Removed test cases that do not respect lifetime/scope constraint.
See discussion in artiq-zynq repo: M-Labs/artiq-zynq#119
Referred to the patch from @dnadlinger. 5faa30a837
 2021-09-10 13:25:12 +08:00
occheung 5985f7efb5 syscall: lower nowrite to inaccessiblememonly 
In the origin implementation, the `nowrite` flag literally means not writing memory at all.
Due to the usage of flags on certain functions, it results in the same issues found in artiq-zynq after optimization passes. (M-Labs/artiq-zynq#119)
A fix wrote by @dnadlinger can resolve this issue. (c1e46cc7c8)
 2021-09-10 13:25:12 +08:00