occheung
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46326716fd
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runtime: bump libfringe, impl ecall abi
See libfringe PR: M-Labs/libfringe#1
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2021-10-16 17:42:24 +08:00 |
occheung
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0a59c889de
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satman/kern: init locked PMP on startup
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2021-10-16 17:42:24 +08:00 |
occheung
|
27a7a96626
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runtime: setup pmp + transfer to user
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2021-10-16 17:42:24 +08:00 |
occheung
|
a0bf11b465
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riscv: impl pmp
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2021-10-16 17:42:24 +08:00 |
occheung
|
790a20edf6
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linker: generate stack guard + symbol
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2021-10-16 17:42:24 +08:00 |
fanmingyu212
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178a86bcda
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master: add an argument to set an experiment subdirectory
Signed-off-by: Mingyu Fan <mingyufan@ucsb.edu>
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2021-10-15 16:54:31 +08:00 |
Sebastien Bourdeauducq
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35d21c98d3
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Revert "runtime: expose rint from libm"
Consistency with NAR3/Zynq where rint is not available.
This reverts commit f5100702f6 .
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2021-10-11 08:12:04 +08:00 |
Sebastien Bourdeauducq
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f5100702f6
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runtime: expose rint from libm
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2021-10-10 20:40:17 +08:00 |
Sebastien Bourdeauducq
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3c1cbf47d2
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phaser: add more slack during init. Closes #1757
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2021-10-10 16:18:55 +08:00 |
Robert Jördens
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3f6bf33298
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fastino: add interpolator support
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2021-10-08 15:47:07 +00:00 |
Harry Ho
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501eb1fa23
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flake: add microscope
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2021-10-08 12:39:35 +08:00 |
Harry Ho
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ea9bc04407
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flake: add jesd204b
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2021-10-08 12:39:35 +08:00 |
occheung
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59065c4663
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alloc_list: support alloc w/ large align
Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
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2021-10-07 12:38:03 +08:00 |
Spaqin
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1894f0f626
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gateware: share RTIOClockMultiplier and fix_serdes_timing_path (#1760)
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2021-10-07 08:19:38 +08:00 |
Sebastien Bourdeauducq
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4bfd010f03
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setup: Python 3.7+
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2021-09-27 17:46:25 +08:00 |
Etienne Wodey
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a8333053c9
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sinara_tester: add device_db and test selection CLI options
Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
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2021-09-27 17:44:50 +08:00 |
occheung
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7a7e17f7e3
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openocd: update and apply 4-byte address support patch
See the relevant commit made in nix-scripts repo.
575ef05cd5
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2021-09-27 09:34:46 +08:00 |
Sebastien Bourdeauducq
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3ed10221d8
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compiler: remove big-endian support. Closes #1590
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2021-09-13 13:40:24 +08:00 |
Sebastien Bourdeauducq
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e8a7a8f41e
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compiler: work around idiotic windoze behavior that causes conda ld.lld not to be found
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2021-09-13 10:40:54 +08:00 |
Sebastien Bourdeauducq
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4834966798
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flake: add jsonschema to dev environment
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2021-09-13 07:39:15 +08:00 |
Sebastien Bourdeauducq
|
7209e6f279
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flake: add cargo-xbuild to dev environment
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2021-09-13 07:20:36 +08:00 |
Sebastien Bourdeauducq
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ffb1e3ec2d
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wavesynth: np.int is deprecated
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2021-09-13 07:02:35 +08:00 |
Sebastien Bourdeauducq
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2d79d824f9
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firmware: remove minor or1k leftovers
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2021-09-12 20:03:37 +08:00 |
Sebastien Bourdeauducq
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1a0c4219ec
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doc: mor1kx -> VexRiscv
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2021-09-12 19:27:00 +08:00 |
Sebastien Bourdeauducq
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2e5c32878f
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flake: add other KC705 NIST builds
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2021-09-10 17:19:32 +08:00 |
occheung
|
a573dcf3f9
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board_misoc/build: use rv32 as target arg
The original rv64 argument was only to match the misoc counterpart.
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2021-09-10 14:11:23 +08:00 |
occheung
|
448974fe11
|
runtime/main: cleanup
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2021-09-10 13:59:53 +08:00 |
occheung
|
b091d8cb66
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kernel: flush cache before mod_init
This could be necessary as redirecting instructions from D$ directly to I$ as it seems.
Related: https://github.com/SpinalHDL/VexRiscv/issues/137
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2021-09-10 13:25:12 +08:00 |
Sebastien Bourdeauducq
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d50e24acb1
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update dependencies
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2021-09-10 13:25:12 +08:00 |
occheung
|
5394d04669
|
test_spi: add delay
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2021-09-10 13:25:12 +08:00 |
occheung
|
b8ed5a0d91
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alloc: fix alignment for riscv32 arch
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2021-09-10 13:25:12 +08:00 |
occheung
|
2213e7ffac
|
ksupp/rtio/exception: fix timestamp
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2021-09-10 13:25:12 +08:00 |
occheung
|
09ffd9de1e
|
dma: fix timestamp fetch
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2021-09-10 13:25:12 +08:00 |
occheung
|
051a14abf2
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rtio/dma: fix endianness
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2021-09-10 13:25:12 +08:00 |
occheung
|
c6ba0f3cf4
|
ksupport: fix dma cslice (ffi)
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2021-09-10 13:25:12 +08:00 |
occheung
|
c812a837ab
|
runtime: enlarge stack size
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2021-09-10 13:25:12 +08:00 |
occheung
|
a596db404d
|
satman: fix cargo xbuild sysroot
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2021-09-10 13:25:12 +08:00 |
Sebastien Bourdeauducq
|
eff7ae5aff
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flake: make llvm-strip in HITL test
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2021-09-10 13:25:12 +08:00 |
Sebastien Bourdeauducq
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c78fbe9bd2
|
flake: make bscanspi bitstreams available in HITL test
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2021-09-10 13:25:12 +08:00 |
Sebastien Bourdeauducq
|
17b9d2fc5a
|
flake: add KC705 HITL test
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2021-09-10 13:25:12 +08:00 |
Sebastien Bourdeauducq
|
5e2664ae7e
|
flake: add openocd
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2021-09-10 13:25:12 +08:00 |
Sebastien Bourdeauducq
|
64ce7e498b
|
flake: make board package a Python package
|
2021-09-10 13:25:12 +08:00 |
Sebastien Bourdeauducq
|
952acce65b
|
flake: build board package on Hydra
|
2021-09-10 13:25:12 +08:00 |
Sebastien Bourdeauducq
|
7ae4b2d9bb
|
flake: update dependencies
|
2021-09-10 13:25:12 +08:00 |
Sebastien Bourdeauducq
|
ce0964e25f
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flake: fix cargo sha256
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2021-09-10 13:25:12 +08:00 |
occheung
|
4fab267593
|
cargo: std dependency hack
|
2021-09-10 13:25:12 +08:00 |
occheung
|
dcbd9f905c
|
cargo: use cargo xbuild
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2021-09-10 13:25:12 +08:00 |
occheung
|
9f6b3f6014
|
firmware: clarify target triple
The lack of compressed instruction support can be inferred from the target triple, literally.
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2021-09-10 13:25:12 +08:00 |
Sebastien Bourdeauducq
|
9697ec33eb
|
flake: update dependencies
|
2021-09-10 13:25:12 +08:00 |
Sebastien Bourdeauducq
|
eee80c7697
|
flake: use improved Rust support in nixpkgs
|
2021-09-10 13:25:12 +08:00 |