16 Commits

Author	SHA1	Message	Date
David Nadlinger	261dc6b933	firmware/runtime: Fix Ext0_Synth0_*to125 log messages	2022-12-02 01:37:56 +00:00
Spaqin	69cddc6b86	rtio_clocking: add warnings for unsupported rtio_clock settings (#1773)	2021-10-28 16:34:22 +08:00
Spaqin	9b1d7e297d	runtime: clock input specification improvements ... closes #1735	2021-10-28 16:21:51 +08:00
Harry Ho	f6d39fd6ba	kc705: revive DRTIO master with updated syntax ... * KC705 master variant now uses Si5324 as synthesiser. * Multi-channel has not been implemented yet.	2021-01-20 15:05:31 +08:00
Sebastien Bourdeauducq	57ee57e7ea	runtime: fix metlino si5324 init (2)	2020-10-14 18:41:56 +08:00
Sebastien Bourdeauducq	ac35548d0f	runtime: fix metlino si5324 init	2020-10-14 12:57:25 +08:00
Sebastien Bourdeauducq	35c61ce24d	si5324: unify N31 settings when used as synthesizer ... Closes #1528	2020-10-12 14:45:52 +08:00
Sebastien Bourdeauducq	9214e0f3e2	firmware: fix Si5324 CKIN selection on Kasli 2.0 ... https://github.com/sinara-hw/Kasli/issues/82#issuecomment-702129805	2020-10-02 20:35:32 +08:00
Sebastien Bourdeauducq	fb0ade77a9	firmware: fix non-DRTIO build	2020-04-10 17:23:17 +08:00
Sebastien Bourdeauducq	61d4614b61	sayma: fix/cleanup DRTIO-DAC sync interaction	2020-04-06 22:34:05 +08:00
Robert Jördens	e0687b77f5	si5324: 10 MHz ext_ref_frequency ... * close #1254 * tested on innsbruck2 kasli variant * sponsored by Uni Innsbruck/AQT Signed-off-by: Robert Jördens <rj@quartiq.de>	2019-11-22 18:29:12 +01:00
Sebastien Bourdeauducq	5a9bb0ecba	runtime: fix incorrect 'RTIO clock failed' report	2019-06-24 23:33:13 +08:00
Sebastien Bourdeauducq	53c778ae2d	runtime: fix previous commit	2019-06-14 15:53:01 +08:00
Sebastien Bourdeauducq	a947867887	runtime: support Kasli Si5324 bypass via rtio_clock=e	2019-06-14 15:48:05 +08:00
Sebastien Bourdeauducq	66a66b03b4	style	2019-06-14 15:29:16 +08:00
Sebastien Bourdeauducq	87ce24e867	runtime: refactor startup and RTIO clocking initialization	2019-06-14 15:26:30 +08:00