whitequark
13ad9b5d08
Allow to dump ARTIQ/LLVM IR for stitched code.
2015-08-08 21:47:20 +03:00
whitequark
ee3f35c608
Improve error message on passing an argument twice.
2015-08-08 21:06:13 +03:00
whitequark
bdcf7f100b
ARTIQIRGenerator: add semantic locs to all other implicitly raised exceptions.
2015-08-08 16:26:53 +03:00
whitequark
acd8d6355f
transforms.ARTIQIRGenerator: IndexError loc should point to "[".
2015-08-08 16:18:57 +03:00
whitequark
96c770190c
Add column marker to ARTIQ exception traceback.
2015-08-08 16:09:47 +03:00
whitequark
27d2390fed
Add zero-cost exception support to runtime and host.
2015-08-08 16:01:31 +03:00
whitequark
1d61e446cb
session.c: ensure session reset on out buffer overrun during RPC.
2015-08-08 14:12:28 +03:00
whitequark
f5ea202e25
session.c: bring back session_ack_{consumed,sent}.
...
These (called session_ack_{data,mem} before) were removed in error.
2015-08-08 14:06:11 +03:00
whitequark
4efae2b67d
Formatting.
2015-08-08 13:48:25 +03:00
whitequark
ecdebc0b8a
session.c: refactor.
2015-08-08 13:21:43 +03:00
whitequark
d6ab567242
coredevice.comm_*: refactor.
2015-08-07 16:44:16 +03:00
whitequark
acc97a74f0
Fix compiler.module.
2015-08-07 14:21:53 +03:00
whitequark
a7633f75c7
Show origin of expansion in diagnostics for synthesized code.
2015-08-07 13:56:18 +03:00
whitequark
50448ef554
Add support for referring to host values in embedded functions.
2015-08-07 13:24:01 +03:00
whitequark
353f454a29
Add basic support for embedded functions with new compiler.
2015-08-07 11:44:49 +03:00
whitequark
b6e2613f77
runtime: avoid spurious error messages.
2015-08-07 11:03:36 +03:00
whitequark
b5cf1e395d
runtime: avoid race condition when running kernel.
...
Also, don't bother passing kernel name: entry point is already
recorded in DT_INIT when the kernel is linked.
2015-08-07 08:51:33 +03:00
whitequark
1a969aa9e4
compiler.transforms.inferencer: accept and ignore @kernel decorator.
2015-08-07 07:54:35 +03:00
whitequark
7562d39750
compiler.module: split off inferencing from Module.__init__.
2015-08-06 08:25:53 +03:00
whitequark
ca52b2fdd0
compiler.transforms.ARTIQIRGenerator: fix typo.
2015-08-06 08:25:53 +03:00
whitequark
98cd4288c1
artiq_personality: cast exception params so that %lld is always valid.
2015-08-06 08:25:53 +03:00
whitequark
722dfef97b
artiq_personality: simplify.
2015-08-06 07:59:15 +03:00
whitequark
8d0222c297
Rename artiq_coreconfig → artiq_coretool; add log subcommand.
2015-08-02 16:40:43 +03:00
whitequark
62fdc75d2d
Integrate libdyld and libunwind.
...
It is currently possible to run the idle experiment, and it
can raise and catch exceptions, but exceptions are not yet
propagated across RPC boundaries.
2015-08-02 15:43:03 +03:00
whitequark
6db93b34e8
artiq_personality: port to device.
2015-08-02 06:34:11 +03:00
whitequark
aae2923c4c
runtime: add lognonl{,_va} functions.
...
The kernels have print(), which prints aggregates (such as
arrays) piece-by-piece, and newlines would interfere.
2015-08-02 06:33:12 +03:00
whitequark
cd294e2986
artiq_personality: avoid unaligned loads.
2015-08-02 06:28:58 +03:00
whitequark
697b78ddf2
Rename {kserver → net_server}.{c,h}.
2015-07-30 13:45:57 +03:00
whitequark
e8943a008c
Rename compiler/{targets/__init__.py → targets.py}.
2015-07-30 10:35:04 +03:00
whitequark
1e3911ed39
Use try..finally in compiler.targets.Target.link.
2015-07-30 10:33:54 +03:00
whitequark
b0185f3917
Add profiling to the performance testbench.
2015-07-29 22:23:22 +03:00
whitequark
d7f9af4bb5
Fix accidentally quadratic code in compiler.ir.Function._add_name.
2015-07-29 21:36:31 +03:00
whitequark
6d8d0ff3f5
Update performance testbench to include time spent in ARTIQ.
2015-07-29 21:28:07 +03:00
whitequark
3b5d3e2b1a
Add a performance measurement testbench.
2015-07-29 21:17:52 +03:00
whitequark
e8c107925c
Implement shared object linking.
2015-07-29 20:35:16 +03:00
whitequark
2cd25f85bf
Rename artiq.compiler.testbench.{module → signature}.
2015-07-29 14:32:34 +03:00
whitequark
3378dd57b8
Fold llvmlite patches into m-labs/llvmlite repository.
2015-07-29 13:54:00 +03:00
whitequark
fd46d8b11e
Merge branch 'master' into new-py2llvm
2015-07-29 12:52:19 +03:00
whitequark
c40ae9dbd3
MiSoC is not built with -fPIC anymore, remove support code for that.
2015-07-29 12:40:46 +03:00
ebbbdcf194
examples/tdr: cleanup
2015-07-28 23:30:26 -06:00
278570faf6
examples: add TDR toy example
2015-07-28 21:36:10 -06:00
90368415a6
ttl: remove timestamp function
...
The general idea is that functions that work with absolute timestamps exist only in machine units versions, to help prevent floating point losses of precision. Time differences should be computed in machine units and then converted, e.g. mu_to_seconds(t2-t1).
This function would have had problems after ~50 days of running the device.
2015-07-29 11:11:16 +08:00
2640a57af3
test/coredevice: let output() settle longer
2015-07-28 16:20:05 -06:00
5f5227f01f
ttl: add timestamp()
2015-07-28 16:20:05 -06:00
e95b66f114
ttl: remove spurious _mu
2015-07-28 16:20:05 -06:00
whitequark
b179430f6b
Specify correct llvmlite branch in installation instructions.
2015-07-28 23:43:07 +03:00
67715f0d2e
pipistrello: only put serdes on the lower ttls
...
this setup is getting a bit power hungry.
pmt0, 1 (rtio channels 0, 1): 4x in and out
ttl0, 1 (rtio channels 2, 3): 4x out
ttl2 (rtio channel 4): 8x out
2015-07-28 12:54:31 -06:00
fb339d294e
serdes_s6: no need to reset
2015-07-28 12:54:31 -06:00
9dfbf07743
pipistrello: use 4x serdes for rtio ttl
...
pipistrello: do not wait for lock on startup
LCK_cycle:6 was added in 6a412f796e1 (mibuild). It waits for _all_
DCM and PLLs to lock (probably irrespective of STARTUP_WAIT).
2015-07-28 12:54:27 -06:00
8e391e2661
kc705: generate 10MHz clock on GPIO SMA
...
For SynthNV and input tests.
2015-07-28 18:56:47 +08:00
