9 Commits

Author	SHA1	Message	Date
Spaqin	17efc28dbe	DRTIO: RTIO/SYS clock merge	2022-12-17 15:39:54 +08:00
mwojcik	f281112779	satman: add 100mhz si5324 settings ... siphaser: add calculated vco for 100mhz comment	2021-12-03 17:19:11 +08:00
mwojcik	eec3ea6589	siphaser: add support for 100mhz rtio	2021-12-03 17:19:11 +08:00
Sebastien Bourdeauducq	d45249197c	siphaser: improve ultrascale clock routing	2019-02-25 23:00:01 +08:00
Sebastien Bourdeauducq	cc58318500	siphaser: autocalibrate skew using RX synchronizer ... * removes the hardcoded, (poorly) manually determined skew value * does not need si5324_clkout_fabric anymore (broken on Sayma RTM due to wrong IO voltage)	2019-01-02 22:29:27 +08:00
Robert Jördens	eb9e9634df	siphaser: support 125 MHz rtio clk ... keep the phase shift increment/decrement at 1/(56*8) rtio_clk cycles	2018-08-29 17:53:48 +00:00
Chris Ballance	07d4145a35	correct documented siphaser VCO frequency [NFC]	2018-06-04 20:53:43 +08:00
Sebastien Bourdeauducq	2426fea3f2	siphaser: support external reference for the freerunning 150MHz	2018-05-12 22:57:11 +08:00
Sebastien Bourdeauducq	916197c4d7	siphaser: cleanup	2018-03-07 11:15:44 +08:00