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14 Commits (master)

Author SHA1 Message Date
Sebastien Bourdeauducq 3027951dd8 integrate new AD9914 driver 
moninj, analyzer, docs, examples, tests.
 2018-05-13 23:29:35 +08:00
Robert Jördens cc70578f1f remove old spi RTIO Phy 2018-03-01 11:19:18 +01:00
Robert Jördens b466a569bf coredevice: export spi2 2018-02-24 09:49:31 +01:00
Sebastien Bourdeauducq 5437f0e3e3 rtio: make sequence errors consistently asychronous 2017-09-29 14:40:06 +08:00
Sebastien Bourdeauducq b74d6fb9ba make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads 2017-03-27 16:32:23 +08:00
Sebastien Bourdeauducq d0af58d122 coredevice: only import common RTIO exceptions 2016-03-19 12:11:47 +08:00
Robert Jördens b0de9ee90a coredevice: add RTIOBusy to __all__ 2016-03-09 12:27:45 +01:00
Robert Jördens 2cb58592ff rtio: add RTIOBusy 2016-03-08 18:04:34 +01:00
Sebastien Bourdeauducq 71105fd0d7 rtio: collision_error -> collision 2016-03-08 15:38:35 +08:00
Robert Jördens 324660ab40 rt2wb, exceptions: remove RTIOTimeout 
Assume that rt2wb transactions either collide and are then
reported (https://github.com/m-labs/artiq/issues/308) or that
they complete and the delay with which they complete does not matter.

If a transaction is ack'ed with a delay because the WB core's downstream
logic is busy, that may lead to a later collision with another WB
transaction.
 2016-03-01 14:44:07 +01:00
Robert Jördens 6c899e6ba6 runtime/rtio: fix rtio_input_wait(), add RTIOTimeout 2016-02-29 19:49:15 +01:00
whitequark 950eaef08c coredevice: re-export more exceptions. 2016-02-24 15:09:22 +00:00
Robert Jördens 765001054d artiq.experiment: merge language and coredevice namespaces 
perl -i -pe 's/^from artiq import \*$/from artiq.experiment import */' your_experiments/*.py

(assuming you skipped the changes form the previous commit)
 2016-01-25 17:24:00 -07:00
Sebastien Bourdeauducq 61a50ee53c reorganize for devices/controllers 2014-10-19 23:51:49 +08:00