mirror of https://github.com/m-labs/artiq.git
sayma: move SYSREF DDMTD to RTM (#795)
This commit is contained in:
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@ -154,15 +154,15 @@ pub mod hmc7043 {
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(true, DAC_CLK_DIV, 0x08, false), // 2: DAC0_CLK
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(true, DAC_CLK_DIV, 0x08, false), // 2: DAC0_CLK
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(true, SYSREF_DIV, 0x01, true), // 3: DAC0_SYSREF
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(true, SYSREF_DIV, 0x01, true), // 3: DAC0_SYSREF
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(true, SYSREF_DIV, 0x10, true), // 4: AMC_FPGA_SYSREF0
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(true, SYSREF_DIV, 0x10, true), // 4: AMC_FPGA_SYSREF0
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(true, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1
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(false, FPGA_CLK_DIV, 0x10, true), // 5: AMC_FPGA_SYSREF1
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(false, 0, 0x10, false), // 6: unused
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(false, 0, 0x10, false), // 6: unused
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(true, SYSREF_DIV, 0x10, true), // 7: RTM_FPGA_SYSREF0
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(true, FPGA_CLK_DIV, 0x10, true), // 7: RTM_FPGA_SYSREF0
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(true, FPGA_CLK_DIV, 0x08, false), // 8: GTP_CLK0_IN
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(true, FPGA_CLK_DIV, 0x08, false), // 8: GTP_CLK0_IN
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(false, 0, 0x10, false), // 9: unused
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(false, 0, 0x10, false), // 9: unused
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(false, 0, 0x10, false), // 10: unused
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(false, 0, 0x10, false), // 10: unused
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(false, 0, 0x08, false), // 11: unused / uFL
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(false, 0, 0x08, false), // 11: unused / uFL
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(false, 0, 0x10, false), // 12: unused
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(false, 0, 0x10, false), // 12: unused
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(false, SYSREF_DIV, 0x10, true), // 13: RTM_FPGA_SYSREF1
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(false, FPGA_CLK_DIV, 0x10, true), // 13: RTM_FPGA_SYSREF1
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];
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];
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fn spi_setup() {
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fn spi_setup() {
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@ -0,0 +1,74 @@
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pub const INIT: u8 = 0x00;
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pub const PRINT_STATUS: u8 = 0x01;
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pub const PRBS: u8 = 0x02;
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pub const STPL: u8 = 0x03;
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pub const SYSREF_DELAY_DAC: u8 = 0x10;
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pub const SYSREF_SLIP: u8 = 0x11;
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pub const SYNC: u8 = 0x12;
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pub const DDMTD_SYSREF_RAW: u8 = 0x20;
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pub const DDMTD_SYSREF: u8 = 0x21;
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fn average_2phases(a: i32, b: i32, modulo: i32) -> i32 {
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let diff = ((a - b + modulo/2 + modulo) % modulo) - modulo/2;
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return (modulo + b + diff/2) % modulo;
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}
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pub fn average_phases(phases: &[i32], modulo: i32) -> i32 {
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if phases.len() == 1 {
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panic!("input array length must be a power of 2");
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} else if phases.len() == 2 {
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average_2phases(phases[0], phases[1], modulo)
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} else {
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let cut = phases.len()/2;
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average_2phases(
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average_phases(&phases[..cut], modulo),
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average_phases(&phases[cut..], modulo),
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modulo)
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}
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}
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pub const RAW_DDMTD_N_SHIFT: i32 = 6;
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pub const RAW_DDMTD_N: i32 = 1 << RAW_DDMTD_N_SHIFT;
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pub const DDMTD_DITHER_BITS: i32 = 1;
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pub const DDMTD_N_SHIFT: i32 = RAW_DDMTD_N_SHIFT + DDMTD_DITHER_BITS;
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pub const DDMTD_N: i32 = 1 << DDMTD_N_SHIFT;
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#[cfg(has_ad9154)]
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use board_misoc::{clock, csr};
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#[cfg(has_ad9154)]
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pub fn init_ddmtd() -> Result<(), &'static str> {
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unsafe {
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csr::sysref_ddmtd::reset_write(1);
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clock::spin_us(1);
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csr::sysref_ddmtd::reset_write(0);
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clock::spin_us(100);
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if csr::sysref_ddmtd::locked_read() != 0 {
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Ok(())
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} else {
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Err("DDMTD helper PLL failed to lock")
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}
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}
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}
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#[cfg(has_ad9154)]
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pub fn measure_ddmdt_phase_raw() -> i32 {
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unsafe { csr::sysref_ddmtd::dt_read() as i32 }
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}
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#[cfg(has_ad9154)]
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pub fn measure_ddmdt_phase() -> i32 {
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const AVG_PRECISION_SHIFT: i32 = 6;
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const AVG_PRECISION: i32 = 1 << AVG_PRECISION_SHIFT;
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const AVG_MOD: i32 = 1 << (RAW_DDMTD_N_SHIFT + AVG_PRECISION_SHIFT + DDMTD_DITHER_BITS);
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let mut measurements = [0; AVG_PRECISION as usize];
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for i in 0..AVG_PRECISION {
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measurements[i as usize] = measure_ddmdt_phase_raw() << (AVG_PRECISION_SHIFT + DDMTD_DITHER_BITS);
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clock::spin_us(10);
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}
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average_phases(&measurements, AVG_MOD) >> AVG_PRECISION_SHIFT
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}
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@ -1,8 +0,0 @@
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pub const INIT: u8 = 0x00;
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pub const PRINT_STATUS: u8 = 0x01;
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pub const PRBS: u8 = 0x02;
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pub const STPL: u8 = 0x03;
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pub const SYSREF_DELAY_DAC: u8 = 0x10;
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pub const SYSREF_SLIP: u8 = 0x11;
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pub const SYNC: u8 = 0x12;
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@ -51,7 +51,7 @@ pub mod jdac {
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use board_artiq::drtioaux;
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use board_artiq::drtioaux;
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use super::jesd;
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use super::jesd;
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use super::super::jdac_requests;
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use super::super::jdac_common;
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pub fn basic_request(dacno: u8, reqno: u8, param: u8) -> Result<u8, &'static str> {
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pub fn basic_request(dacno: u8, reqno: u8, param: u8) -> Result<u8, &'static str> {
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if let Err(e) = drtioaux::send(1, &drtioaux::Packet::JdacBasicRequest {
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if let Err(e) = drtioaux::send(1, &drtioaux::Packet::JdacBasicRequest {
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@ -95,24 +95,24 @@ pub mod jdac {
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return Err("JESD core PHY not done");
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return Err("JESD core PHY not done");
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}
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}
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basic_request(dacno, jdac_requests::INIT, 0)?;
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basic_request(dacno, jdac_common::INIT, 0)?;
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// JESD ready depends on JSYNC being valid, so DAC init needs to happen first
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// JESD ready depends on JSYNC being valid, so DAC init needs to happen first
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if !jesd::ready(dacno) {
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if !jesd::ready(dacno) {
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error!("JESD core reported not ready, sending DAC status print request");
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error!("JESD core reported not ready, sending DAC status print request");
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basic_request(dacno, jdac_requests::PRINT_STATUS, 0)?;
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basic_request(dacno, jdac_common::PRINT_STATUS, 0)?;
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return Err("JESD core reported not ready");
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return Err("JESD core reported not ready");
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}
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}
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jesd::prbs(dacno, true);
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jesd::prbs(dacno, true);
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basic_request(dacno, jdac_requests::PRBS, 0)?;
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basic_request(dacno, jdac_common::PRBS, 0)?;
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jesd::prbs(dacno, false);
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jesd::prbs(dacno, false);
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jesd::stpl(dacno, true);
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jesd::stpl(dacno, true);
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basic_request(dacno, jdac_requests::STPL, 0)?;
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basic_request(dacno, jdac_common::STPL, 0)?;
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jesd::stpl(dacno, false);
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jesd::stpl(dacno, false);
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basic_request(dacno, jdac_requests::INIT, 0)?;
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basic_request(dacno, jdac_common::INIT, 0)?;
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clock::spin_us(5000);
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clock::spin_us(5000);
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if !jesd::jsync(dacno) {
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if !jesd::jsync(dacno) {
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@ -130,7 +130,7 @@ pub mod jesd204sync {
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use board_misoc::{csr, clock, config};
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use board_misoc::{csr, clock, config};
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use super::jdac;
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use super::jdac;
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use super::super::jdac_requests;
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use super::super::jdac_common;
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const HMC7043_ANALOG_DELAY_RANGE: u8 = 24;
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const HMC7043_ANALOG_DELAY_RANGE: u8 = 24;
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@ -138,7 +138,7 @@ pub mod jesd204sync {
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const SYSREF_DIV: u16 = 256; // Keep in sync with hmc830_7043.rs
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const SYSREF_DIV: u16 = 256; // Keep in sync with hmc830_7043.rs
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fn hmc7043_sysref_delay_dac(dacno: u8, phase_offset: u8) -> Result<(), &'static str> {
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fn hmc7043_sysref_delay_dac(dacno: u8, phase_offset: u8) -> Result<(), &'static str> {
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match jdac::basic_request(dacno, jdac_requests::SYSREF_DELAY_DAC, phase_offset) {
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match jdac::basic_request(dacno, jdac_common::SYSREF_DELAY_DAC, phase_offset) {
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Ok(_) => Ok(()),
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Ok(_) => Ok(()),
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Err(e) => Err(e)
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Err(e) => Err(e)
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}
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}
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@ -146,90 +146,43 @@ pub mod jesd204sync {
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fn hmc7043_sysref_slip() -> Result<(), &'static str> {
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fn hmc7043_sysref_slip() -> Result<(), &'static str> {
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match jdac::basic_request(0, jdac_requests::SYSREF_SLIP, 0) {
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match jdac::basic_request(0, jdac_common::SYSREF_SLIP, 0) {
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Ok(_) => Ok(()),
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Ok(_) => Ok(()),
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Err(e) => Err(e)
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Err(e) => Err(e)
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}
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}
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}
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}
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fn ad9154_sync(dacno: u8) -> Result<bool, &'static str> {
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fn ad9154_sync(dacno: u8) -> Result<bool, &'static str> {
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match jdac::basic_request(dacno, jdac_requests::SYNC, 0) {
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match jdac::basic_request(dacno, jdac_common::SYNC, 0) {
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Ok(0) => Ok(false),
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Ok(0) => Ok(false),
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Ok(_) => Ok(true),
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Ok(_) => Ok(true),
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Err(e) => Err(e)
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Err(e) => Err(e)
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}
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}
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}
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}
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fn average_2phases(a: i32, b: i32, modulo: i32) -> i32 {
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let diff = ((a - b + modulo/2 + modulo) % modulo) - modulo/2;
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fn measure_ddmdt_phase_raw() -> Result<i32, &'static str> {
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return (modulo + b + diff/2) % modulo;
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Ok(jdac::basic_request(0, jdac_common::DDMTD_SYSREF_RAW, 0)? as i32)
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}
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}
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fn average_phases(phases: &[i32], modulo: i32) -> i32 {
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fn measure_ddmdt_phase() -> Result<i32, &'static str> {
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if phases.len() == 1 {
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Ok(jdac::basic_request(0, jdac_common::DDMTD_SYSREF, 0)? as i32)
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panic!("input array length must be a power of 2");
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} else if phases.len() == 2 {
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average_2phases(phases[0], phases[1], modulo)
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} else {
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let cut = phases.len()/2;
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average_2phases(
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average_phases(&phases[..cut], modulo),
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average_phases(&phases[cut..], modulo),
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modulo)
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}
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}
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const RAW_DDMTD_N_SHIFT: i32 = 6;
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const RAW_DDMTD_N: i32 = 1 << RAW_DDMTD_N_SHIFT;
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const DDMTD_DITHER_BITS: i32 = 1;
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const DDMTD_N_SHIFT: i32 = RAW_DDMTD_N_SHIFT + DDMTD_DITHER_BITS;
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const DDMTD_N: i32 = 1 << DDMTD_N_SHIFT;
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fn init_ddmtd() -> Result<(), &'static str> {
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unsafe {
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csr::sysref_ddmtd::reset_write(1);
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clock::spin_us(1);
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csr::sysref_ddmtd::reset_write(0);
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clock::spin_us(100);
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if csr::sysref_ddmtd::locked_read() != 0 {
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Ok(())
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} else {
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Err("DDMTD helper PLL failed to lock")
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}
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}
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}
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fn measure_ddmdt_phase_raw() -> i32 {
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unsafe { csr::sysref_ddmtd::dt_read() as i32 }
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}
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fn measure_ddmdt_phase() -> i32 {
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const AVG_PRECISION_SHIFT: i32 = 6;
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const AVG_PRECISION: i32 = 1 << AVG_PRECISION_SHIFT;
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const AVG_MOD: i32 = 1 << (RAW_DDMTD_N_SHIFT + AVG_PRECISION_SHIFT + DDMTD_DITHER_BITS);
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let mut measurements = [0; AVG_PRECISION as usize];
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for i in 0..AVG_PRECISION {
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measurements[i as usize] = measure_ddmdt_phase_raw() << (AVG_PRECISION_SHIFT + DDMTD_DITHER_BITS);
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clock::spin_us(10);
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}
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average_phases(&measurements, AVG_MOD) >> AVG_PRECISION_SHIFT
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}
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}
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fn test_ddmtd_stability(raw: bool, tolerance: i32) -> Result<(), &'static str> {
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fn test_ddmtd_stability(raw: bool, tolerance: i32) -> Result<(), &'static str> {
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info!("testing DDMTD stability (raw={}, tolerance={})...", raw, tolerance);
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info!("testing DDMTD stability (raw={}, tolerance={})...", raw, tolerance);
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let modulo = if raw { RAW_DDMTD_N } else { DDMTD_N };
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let modulo = if raw { jdac_common::RAW_DDMTD_N } else { jdac_common::DDMTD_N };
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let measurement = if raw { measure_ddmdt_phase_raw } else { measure_ddmdt_phase };
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let measurement = if raw { measure_ddmdt_phase_raw } else { measure_ddmdt_phase };
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let ntests = if raw { 15000 } else { 150 };
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let ntests = if raw { 150 } else { 15 };
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let mut max_pkpk = 0;
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let mut max_pkpk = 0;
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for _ in 0..32 {
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for _ in 0..32 {
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// If we are near the edges, wraparound can throw off the simple min/max computation.
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// If we are near the edges, wraparound can throw off the simple min/max computation.
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// In this case, add an offset to get near the center.
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// In this case, add an offset to get near the center.
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let quadrant = measure_ddmdt_phase();
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let quadrant = measure_ddmdt_phase()?;
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let center_offset =
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let center_offset =
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if quadrant < DDMTD_N/4 || quadrant > 3*DDMTD_N/4 {
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if quadrant < jdac_common::DDMTD_N/4 || quadrant > 3*jdac_common::DDMTD_N/4 {
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modulo/2
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modulo/2
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} else {
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} else {
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0
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0
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@ -238,7 +191,7 @@ pub mod jesd204sync {
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let mut min = modulo;
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let mut min = modulo;
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let mut max = 0;
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let mut max = 0;
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for _ in 0..ntests {
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for _ in 0..ntests {
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let m = (measurement() + center_offset) % modulo;
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let m = (measurement()? + center_offset) % modulo;
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if m < min {
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if m < min {
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min = m;
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min = m;
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}
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}
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@ -268,11 +221,11 @@ pub mod jesd204sync {
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let tolerance = 1;
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let tolerance = 1;
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info!("testing HMC7043 SYSREF slip against DDMTD...");
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info!("testing HMC7043 SYSREF slip against DDMTD...");
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let mut old_phase = measure_ddmdt_phase();
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let mut old_phase = measure_ddmdt_phase()?;
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for _ in 0..1024 {
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for _ in 0..1024 {
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hmc7043_sysref_slip();
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hmc7043_sysref_slip();
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let phase = measure_ddmdt_phase();
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let phase = measure_ddmdt_phase()?;
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let step = (DDMTD_N + old_phase - phase) % DDMTD_N;
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let step = (jdac_common::DDMTD_N + old_phase - phase) % jdac_common::DDMTD_N;
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if (step - expected_step).abs() > tolerance {
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if (step - expected_step).abs() > tolerance {
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error!(" ...got unexpected step: {} ({} -> {})", step, old_phase, phase);
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error!(" ...got unexpected step: {} ({} -> {})", step, old_phase, phase);
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return Err("HMC7043 SYSREF slip produced unexpected DDMTD step");
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return Err("HMC7043 SYSREF slip produced unexpected DDMTD step");
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@ -295,7 +248,7 @@ pub mod jesd204sync {
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const SYSREF_SH_PRECISION_SHIFT: i32 = 5;
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const SYSREF_SH_PRECISION_SHIFT: i32 = 5;
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const SYSREF_SH_PRECISION: i32 = 1 << SYSREF_SH_PRECISION_SHIFT;
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const SYSREF_SH_PRECISION: i32 = 1 << SYSREF_SH_PRECISION_SHIFT;
|
||||||
const SYSREF_SH_MOD: i32 = 1 << (DDMTD_N_SHIFT + SYSREF_SH_PRECISION_SHIFT);
|
const SYSREF_SH_MOD: i32 = 1 << (jdac_common::DDMTD_N_SHIFT + SYSREF_SH_PRECISION_SHIFT);
|
||||||
|
|
||||||
#[derive(Default)]
|
#[derive(Default)]
|
||||||
struct SysrefShLimits {
|
struct SysrefShLimits {
|
||||||
|
@ -318,7 +271,7 @@ pub mod jesd204sync {
|
||||||
}
|
}
|
||||||
|
|
||||||
let current = sysref_sh_error();
|
let current = sysref_sh_error();
|
||||||
let phase = measure_ddmdt_phase();
|
let phase = measure_ddmdt_phase()?;
|
||||||
if current && !previous && rising_n < SYSREF_SH_PRECISION {
|
if current && !previous && rising_n < SYSREF_SH_PRECISION {
|
||||||
ret.rising_phases[rising_n as usize] = phase << SYSREF_SH_PRECISION_SHIFT;
|
ret.rising_phases[rising_n as usize] = phase << SYSREF_SH_PRECISION_SHIFT;
|
||||||
rising_n += 1;
|
rising_n += 1;
|
||||||
|
@ -335,7 +288,7 @@ pub mod jesd204sync {
|
||||||
fn max_phase_deviation(average: i32, phases: &[i32]) -> i32 {
|
fn max_phase_deviation(average: i32, phases: &[i32]) -> i32 {
|
||||||
let mut ret = 0;
|
let mut ret = 0;
|
||||||
for phase in phases.iter() {
|
for phase in phases.iter() {
|
||||||
let deviation = (phase - average + DDMTD_N) % DDMTD_N;
|
let deviation = (phase - average + jdac_common::DDMTD_N) % jdac_common::DDMTD_N;
|
||||||
if deviation > ret {
|
if deviation > ret {
|
||||||
ret = deviation;
|
ret = deviation;
|
||||||
}
|
}
|
||||||
|
@ -345,7 +298,7 @@ pub mod jesd204sync {
|
||||||
|
|
||||||
fn reach_sysref_ddmtd_target(target: i32, tolerance: i32) -> Result<i32, &'static str> {
|
fn reach_sysref_ddmtd_target(target: i32, tolerance: i32) -> Result<i32, &'static str> {
|
||||||
for _ in 0..1024 {
|
for _ in 0..1024 {
|
||||||
let delta = (measure_ddmdt_phase() - target + DDMTD_N) % DDMTD_N;
|
let delta = (measure_ddmdt_phase()? - target + jdac_common::DDMTD_N) % jdac_common::DDMTD_N;
|
||||||
if delta <= tolerance {
|
if delta <= tolerance {
|
||||||
return Ok(delta)
|
return Ok(delta)
|
||||||
}
|
}
|
||||||
|
@ -360,11 +313,11 @@ pub mod jesd204sync {
|
||||||
if rising_average < falling_average {
|
if rising_average < falling_average {
|
||||||
(rising_average + falling_average)/2
|
(rising_average + falling_average)/2
|
||||||
} else {
|
} else {
|
||||||
((falling_average - (DDMTD_N - rising_average))/2 + DDMTD_N) % DDMTD_N
|
((falling_average - (jdac_common::DDMTD_N - rising_average))/2 + jdac_common::DDMTD_N) % jdac_common::DDMTD_N
|
||||||
};
|
};
|
||||||
info!(" SYSREF calibration coarse target: {}", coarse_target);
|
info!(" SYSREF calibration coarse target: {}", coarse_target);
|
||||||
reach_sysref_ddmtd_target(coarse_target, 8)?;
|
reach_sysref_ddmtd_target(coarse_target, 8)?;
|
||||||
let target = measure_ddmdt_phase();
|
let target = measure_ddmdt_phase()?;
|
||||||
info!(" ...done, target={}", target);
|
info!(" ...done, target={}", target);
|
||||||
Ok(target)
|
Ok(target)
|
||||||
}
|
}
|
||||||
|
@ -447,15 +400,14 @@ pub mod jesd204sync {
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
|
pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
|
||||||
init_ddmtd()?;
|
|
||||||
test_ddmtd_stability(true, 4)?;
|
test_ddmtd_stability(true, 4)?;
|
||||||
test_ddmtd_stability(false, 1)?;
|
test_ddmtd_stability(false, 1)?;
|
||||||
test_slip_ddmtd()?;
|
test_slip_ddmtd()?;
|
||||||
|
|
||||||
info!("determining SYSREF S/H limits...");
|
info!("determining SYSREF S/H limits...");
|
||||||
let sysref_sh_limits = measure_sysref_sh_limits()?;
|
let sysref_sh_limits = measure_sysref_sh_limits()?;
|
||||||
let rising_average = average_phases(&sysref_sh_limits.rising_phases, SYSREF_SH_MOD);
|
let rising_average = jdac_common::average_phases(&sysref_sh_limits.rising_phases, SYSREF_SH_MOD);
|
||||||
let falling_average = average_phases(&sysref_sh_limits.falling_phases, SYSREF_SH_MOD);
|
let falling_average = jdac_common::average_phases(&sysref_sh_limits.falling_phases, SYSREF_SH_MOD);
|
||||||
let rising_max_deviation = max_phase_deviation(rising_average, &sysref_sh_limits.rising_phases);
|
let rising_max_deviation = max_phase_deviation(rising_average, &sysref_sh_limits.rising_phases);
|
||||||
let falling_max_deviation = max_phase_deviation(falling_average, &sysref_sh_limits.falling_phases);
|
let falling_max_deviation = max_phase_deviation(falling_average, &sysref_sh_limits.falling_phases);
|
||||||
|
|
||||||
|
|
|
@ -22,7 +22,7 @@ mod repeater;
|
||||||
#[cfg(has_jdcg)]
|
#[cfg(has_jdcg)]
|
||||||
mod jdcg;
|
mod jdcg;
|
||||||
#[cfg(any(has_ad9154, has_jdcg))]
|
#[cfg(any(has_ad9154, has_jdcg))]
|
||||||
pub mod jdac_requests;
|
pub mod jdac_common;
|
||||||
|
|
||||||
fn drtiosat_reset(reset: bool) {
|
fn drtiosat_reset(reset: bool) {
|
||||||
unsafe {
|
unsafe {
|
||||||
|
@ -306,13 +306,13 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
|
||||||
#[cfg(rtio_frequency = "150.0")]
|
#[cfg(rtio_frequency = "150.0")]
|
||||||
const LINERATE: u64 = 6_000_000_000;
|
const LINERATE: u64 = 6_000_000_000;
|
||||||
match _reqno {
|
match _reqno {
|
||||||
jdac_requests::INIT => (board_artiq::ad9154::setup(_dacno, LINERATE).is_ok(), 0),
|
jdac_common::INIT => (board_artiq::ad9154::setup(_dacno, LINERATE).is_ok(), 0),
|
||||||
jdac_requests::PRINT_STATUS => { board_artiq::ad9154::status(_dacno); (true, 0) },
|
jdac_common::PRINT_STATUS => { board_artiq::ad9154::status(_dacno); (true, 0) },
|
||||||
jdac_requests::PRBS => (board_artiq::ad9154::prbs(_dacno).is_ok(), 0),
|
jdac_common::PRBS => (board_artiq::ad9154::prbs(_dacno).is_ok(), 0),
|
||||||
jdac_requests::STPL => (board_artiq::ad9154::stpl(_dacno, 4, 2).is_ok(), 0),
|
jdac_common::STPL => (board_artiq::ad9154::stpl(_dacno, 4, 2).is_ok(), 0),
|
||||||
jdac_requests::SYSREF_DELAY_DAC => { board_artiq::hmc830_7043::hmc7043::sysref_delay_dac(_dacno, _param); (true, 0) },
|
jdac_common::SYSREF_DELAY_DAC => { board_artiq::hmc830_7043::hmc7043::sysref_delay_dac(_dacno, _param); (true, 0) },
|
||||||
jdac_requests::SYSREF_SLIP => { board_artiq::hmc830_7043::hmc7043::sysref_slip(); (true, 0) },
|
jdac_common::SYSREF_SLIP => { board_artiq::hmc830_7043::hmc7043::sysref_slip(); (true, 0) },
|
||||||
jdac_requests::SYNC => {
|
jdac_common::SYNC => {
|
||||||
match board_artiq::ad9154::sync(_dacno) {
|
match board_artiq::ad9154::sync(_dacno) {
|
||||||
Ok(false) => (true, 0),
|
Ok(false) => (true, 0),
|
||||||
Ok(true) => (true, 1),
|
Ok(true) => (true, 1),
|
||||||
|
@ -321,7 +321,9 @@ fn process_aux_packet(_repeaters: &mut [repeater::Repeater],
|
||||||
(false, 0)
|
(false, 0)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
},
|
||||||
|
jdac_common::DDMTD_SYSREF_RAW => (true, jdac_common::measure_ddmdt_phase_raw() as u8),
|
||||||
|
jdac_common::DDMTD_SYSREF => (true, jdac_common::measure_ddmdt_phase() as u8),
|
||||||
_ => (false, 0)
|
_ => (false, 0)
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
@ -472,6 +474,7 @@ pub extern fn main() -> i32 {
|
||||||
hmc830_7043::init().expect("cannot initialize HMC830/7043");
|
hmc830_7043::init().expect("cannot initialize HMC830/7043");
|
||||||
#[cfg(has_ad9154)]
|
#[cfg(has_ad9154)]
|
||||||
{
|
{
|
||||||
|
jdac_common::init_ddmtd().expect("failed to initialize SYSREF DDMTD core");
|
||||||
for dacno in 0..csr::CONFIG_AD9154_COUNT {
|
for dacno in 0..csr::CONFIG_AD9154_COUNT {
|
||||||
board_artiq::ad9154::reset_and_detect(dacno as u8).expect("AD9154 DAC not detected");
|
board_artiq::ad9154::reset_and_detect(dacno as u8).expect("AD9154 DAC not detected");
|
||||||
}
|
}
|
||||||
|
|
|
@ -311,12 +311,6 @@ class Satellite(SatelliteBase):
|
||||||
self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref)
|
self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref)
|
||||||
self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref)
|
self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref)
|
||||||
|
|
||||||
# DDMTD
|
|
||||||
# https://github.com/sinara-hw/Sayma_RTM/issues/68
|
|
||||||
sysref_pads = platform.request("amc_fpga_sysref", 1)
|
|
||||||
self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(sysref_pads, self.rtio_clk_freq)
|
|
||||||
self.csr_devices.append("sysref_ddmtd")
|
|
||||||
|
|
||||||
|
|
||||||
class SimpleSatellite(SatelliteBase):
|
class SimpleSatellite(SatelliteBase):
|
||||||
def __init__(self, **kwargs):
|
def __init__(self, **kwargs):
|
||||||
|
|
|
@ -16,6 +16,7 @@ from misoc.targets.sayma_rtm import BaseSoC, soc_sayma_rtm_args, soc_sayma_rtm_a
|
||||||
from misoc.integration.builder import Builder, builder_args, builder_argdict
|
from misoc.integration.builder import Builder, builder_args, builder_argdict
|
||||||
|
|
||||||
from artiq.gateware import rtio
|
from artiq.gateware import rtio
|
||||||
|
from artiq.gateware import jesd204_tools
|
||||||
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series
|
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series
|
||||||
from artiq.gateware.drtio.transceiver import gtp_7series
|
from artiq.gateware.drtio.transceiver import gtp_7series
|
||||||
from artiq.gateware.drtio.siphaser import SiPhaser7Series
|
from artiq.gateware.drtio.siphaser import SiPhaser7Series
|
||||||
|
@ -257,6 +258,15 @@ class Satellite(_SatelliteBase):
|
||||||
platform.request("hmc7043_out_en"))
|
platform.request("hmc7043_out_en"))
|
||||||
self.csr_devices.append("hmc7043_out_en")
|
self.csr_devices.append("hmc7043_out_en")
|
||||||
|
|
||||||
|
# DDMTD
|
||||||
|
sysref_pads = platform.request("rtm_fpga_sysref", 0)
|
||||||
|
self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(sysref_pads, self.rtio_clk_freq)
|
||||||
|
self.csr_devices.append("sysref_ddmtd")
|
||||||
|
platform.add_false_path_constraints(
|
||||||
|
self.sysref_ddmtd.cd_helper.clk, self.drtio_transceiver.gtps[0].txoutclk)
|
||||||
|
platform.add_false_path_constraints(
|
||||||
|
self.sysref_ddmtd.cd_helper.clk, self.crg.cd_sys.clk)
|
||||||
|
|
||||||
|
|
||||||
class SatmanSoCBuilder(Builder):
|
class SatmanSoCBuilder(Builder):
|
||||||
def __init__(self, *args, **kwargs):
|
def __init__(self, *args, **kwargs):
|
||||||
|
|
Loading…
Reference in New Issue