M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-26 03:38:25 +08:00
Code Issues Projects Releases Wiki Activity

drtioaux: add analyzer related messages

Browse Source
This commit is contained in:
mwojcik 2023-05-10 15:56:37 +08:00 committed by Sébastien Bourdeauducq
parent c36b6b3b65
commit fdca1ab7fc
1 changed files with 32 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
artiq/firmware/libproto_artiq/drtioaux_proto.rs
View File

@ -14,8 +14,8 @@ impl<T> From<IoError<T>> for Error<T> {
}
}
/* 512 (max size) - 4 (CRC) - 1 (packet ID) - 1 (destination) - 4 (trace ID) - 1 (last) - 2 (length) */
pub const DMA_TRACE_MAX_SIZE: usize = 499;
pub const DMA_TRACE_MAX_SIZE: usize = /*max size*/512 - /*CRC*/4 - /*packet ID*/1 - /*trace ID*/4 - /*last*/1 -/*length*/2;
pub const ANALYZER_MAX_SIZE: usize = /*max size*/512 - /*CRC*/4 - /*packet ID*/1 - /*last*/1 - /*length*/2;
#[derive(PartialEq, Debug)]
pub enum Packet {
@ -58,6 +58,9 @@ pub enum Packet {
SpiReadReply { succeeded: bool, data: u32 },
SpiBasicReply { succeeded: bool },
AnalyzerRequest { destination: u8 },
AnalyzerData { last: bool, length: u16, data: [u8; ANALYZER_MAX_SIZE]},
DmaAddTraceRequest { destination: u8, id: u32, last: bool, length: u16, trace: [u8; DMA_TRACE_MAX_SIZE] },
DmaAddTraceReply { succeeded: bool },
DmaRemoveTraceRequest { destination: u8, id: u32 },
@ -65,7 +68,6 @@ pub enum Packet {
DmaPlaybackRequest { destination: u8, id: u32, timestamp: u64 },
DmaPlaybackReply { succeeded: bool },
DmaPlaybackStatus { destination: u8, id: u32, error: u8, channel: u32, timestamp: u64 }
}
impl Packet {
@ -197,6 +199,22 @@ impl Packet {
succeeded: reader.read_bool()?
},
0xa0 => Packet::AnalyzerRequest {
destination: reader.read_u8()?
},
0xa1 => {
let last = reader.read_bool()?;
let length = reader.read_u16()?;
let mut data: [u8; ANALYZER_MAX_SIZE] = [0; ANALYZER_MAX_SIZE];
reader.read_exact(&mut trace[0..length as usize])?;
Packet::AnalyzerData {
last: last,
length: length,
data: data
}
}
0xb0 => {
let destination = reader.read_u8()?;
let id = reader.read_u32()?;
@ -397,6 +415,17 @@ impl Packet {
writer.write_bool(succeeded)?;
},
Packet::AnalyzerRequest { destination } => {
writer.write_u8(0xa0)?;
writer.write_u8(destination)?;
},
Packet::AnalyzerData { last, length, data } => {
writer.write_u8(0xa1)?;
writer.write_bool(last)?;
writer.write_u16(length)?;
writer.write_all(&data[0..length as usize])?;
},
Packet::DmaAddTraceRequest { destination, id, last, trace, length } => {
writer.write_u8(0xb0)?;
writer.write_u8(destination)?;