kernel: use vexriscv

This commit is contained in:
occheung 2021-08-17 11:07:18 +08:00
parent 9adab6c817
commit fc42d053d9
1 changed files with 3 additions and 3 deletions

View File

@ -1,7 +1,7 @@
from migen import *
from misoc.interconnect.csr import *
from misoc.interconnect import wishbone
from misoc.cores import mor1kx
from misoc.cores import vexriscv
from misoc.integration.wb_slaves import WishboneSlaveManager
@ -23,9 +23,9 @@ class KernelCPU(Module):
self.cd_sys_kernel.rst.eq(self._reset.storage)
]
self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(
mor1kx.MOR1KX(
vexriscv.VexRiscv(
platform,
OPTION_RESET_PC=exec_address))
exec_address))
# DRAM access
self.wb_sdram = wishbone.Interface()