drtio: reorganize RX synchronizers

artiq/gateware/drtio/core.py

@@ -1,7 +1,6 @@
 from types import SimpleNamespace
 
 from migen import *
-from migen.genlib.cdc import ElasticBuffer
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from misoc.interconnect.csr import *
 
@@ -10,6 +9,7 @@ from artiq.gateware.rtio.input_collector import *
 from artiq.gateware.drtio import (link_layer, aux_controller,
                                   rt_packet_satellite, rt_errors_satellite,
                                   rt_packet_master, rt_controller_master)
+from artiq.gateware.drtio.rx_synchronizer import GenericRXSynchronizer
 
 
 class ChannelInterface:
@@ -29,29 +29,6 @@ class TransceiverInterface(AutoCSR):
         self.channels = channel_interfaces
 
 
-class GenericRXSynchronizer(Module):
-    """Simple RX synchronizer based on the portable Migen elastic buffer.
-
-    Introduces timing non-determinism in the satellite RX path, e.g.
-    echo_request/echo_reply RTT and TSC sync, but useful for testing.
-    """
-    def __init__(self):
-        self.signals = []
-
-    def resync(self, signal):
-        synchronized = Signal.like(signal, related=signal)
-        self.signals.append((signal, synchronized))
-        return synchronized
-
-    def do_finalize(self):
-        eb = ElasticBuffer(sum(len(s[0]) for s in self.signals), 4, "rtio_rx", "rtio")
-        self.submodules += eb
-        self.comb += [
-            eb.din.eq(Cat(*[s[0] for s in self.signals])),
-            Cat(*[s[1] for s in self.signals]).eq(eb.dout)
-        ]
-
-
 class DRTIOSatellite(Module):
     def __init__(self, chanif, channels, rx_synchronizer=None, fine_ts_width=3,
                  lane_count=8, fifo_depth=128):

artiq/gateware/drtio/rx_synchronizer.py

@@ -1,4 +1,28 @@
 from migen import *
+from migen.genlib.cdc import ElasticBuffer
+
+
+class GenericRXSynchronizer(Module):
+    """Simple RX synchronizer based on the portable Migen elastic buffer.
+
+    Introduces timing non-determinism in the satellite RX path, e.g.
+    echo_request/echo_reply RTT and TSC sync, but useful for testing.
+    """
+    def __init__(self):
+        self.signals = []
+
+    def resync(self, signal):
+        synchronized = Signal.like(signal, related=signal)
+        self.signals.append((signal, synchronized))
+        return synchronized
+
+    def do_finalize(self):
+        eb = ElasticBuffer(sum(len(s[0]) for s in self.signals), 4, "rtio_rx", "rtio")
+        self.submodules += eb
+        self.comb += [
+            eb.din.eq(Cat(*[s[0] for s in self.signals])),
+            Cat(*[s[1] for s in self.signals]).eq(eb.dout)
+        ]
 
 
 class XilinxRXSynchronizer(Module):

artiq/gateware/targets/kasli.py

@@ -21,7 +21,7 @@ from artiq.gateware.amp import AMPSoC
 from artiq.gateware import rtio
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2
 from artiq.gateware.drtio.transceiver import gtp_7series
-from artiq.gateware.drtio.xilinx_rx_synchronizer import XilinxRXSynchronizer
+from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
 from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
 from artiq.build_soc import build_artiq_soc
 from artiq import __version__ as artiq_version

artiq/gateware/targets/sayma_amc.py

@@ -33,7 +33,7 @@ from artiq.gateware import remote_csr
 from artiq.gateware import rtio
 from artiq.gateware.rtio.phy import ttl_simple, sawg
 from artiq.gateware.drtio.transceiver import gth_ultrascale
-from artiq.gateware.drtio.xilinx_rx_synchronizer import XilinxRXSynchronizer
+from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
 from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
 from artiq.build_soc import build_artiq_soc
 from artiq import __version__ as artiq_version