mirror of https://github.com/m-labs/artiq.git
487 lines
19 KiB
Python
Executable File
487 lines
19 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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import os
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from collections import namedtuple
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import warnings
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.io import DifferentialInput
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from microscope import *
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from misoc.cores import gpio
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from misoc.cores.slave_fpga import SlaveFPGA
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from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.interconnect import stream
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from misoc.interconnect.csr import *
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from misoc.targets.sayma_amc import BaseSoC, MiniSoC
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from jesd204b.common import (JESD204BTransportSettings,
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JESD204BPhysicalSettings,
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JESD204BSettings)
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from jesd204b.phy.gth import GTHChannelPLL as JESD204BGTHChannelPLL
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from jesd204b.phy import JESD204BPhyTX
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from jesd204b.core import JESD204BCoreTX
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from jesd204b.core import JESD204BCoreTXControl
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import serwb
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from artiq.gateware import remote_csr
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, sawg
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from artiq.gateware.drtio.transceiver import gth_ultrascale
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import DRTIOMaster, DRTIOSatellite
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from artiq.build_soc import build_artiq_soc
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from artiq import __version__ as artiq_version
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PhyPads = namedtuple("PhyPads", "txp txn")
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to_jesd = ClockDomainsRenamer("jesd")
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class AD9154CRG(Module, AutoCSR):
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linerate = int(6e9)
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refclk_freq = int(150e6)
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fabric_freq = int(125e6)
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def __init__(self, platform):
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self.jreset = CSRStorage(reset=1)
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self.jref = Signal()
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self.refclk = Signal()
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refclk2 = Signal()
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self.clock_domains.cd_jesd = ClockDomain()
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refclk_pads = platform.request("dac_refclk", 0)
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platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq)
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self.specials += [
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Instance("IBUFDS_GTE3", i_CEB=0, p_REFCLK_HROW_CK_SEL=0b00,
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i_I=refclk_pads.p, i_IB=refclk_pads.n,
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o_O=self.refclk, o_ODIV2=refclk2),
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Instance("BUFG_GT", i_I=refclk2, o_O=self.cd_jesd.clk),
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AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage),
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]
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jref = platform.request("dac_sysref")
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self.specials += DifferentialInput(jref.p, jref.n, self.jref)
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class AD9154JESD(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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ps = JESD204BPhysicalSettings(l=8, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=2, k=16, cs=0)
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settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_pads = platform.request("dac_jesd", dac)
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phys = []
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for i in range(len(jesd_pads.txp)):
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cpll = JESD204BGTHChannelPLL(
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jesd_crg.refclk, jesd_crg.refclk_freq, jesd_crg.linerate)
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self.submodules += cpll
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#print(cpll)
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phy = JESD204BPhyTX(
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cpll, PhyPads(jesd_pads.txp[i], jesd_pads.txn[i]),
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jesd_crg.fabric_freq, transceiver="gth")
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platform.add_period_constraint(phy.transmitter.cd_tx.clk,
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40*1e9/jesd_crg.linerate)
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platform.add_false_path_constraints(
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sys_crg.cd_sys.clk,
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jesd_crg.cd_jesd.clk,
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phy.transmitter.cd_tx.clk)
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phys.append(phy)
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self.submodules.core = core = to_jesd(JESD204BCoreTX(
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phys, settings, converter_data_width=64))
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self.submodules.control = control = to_jesd(JESD204BCoreTXControl(core))
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core.register_jsync(platform.request("dac_sync", dac))
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core.register_jref(jesd_crg.jref)
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class AD9154(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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self.submodules.jesd = AD9154JESD(platform, sys_crg, jesd_crg, dac)
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self.sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
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self.submodules += self.sawgs
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for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
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assert len(Cat(ch.o)) == len(conv)
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self.sync.jesd += conv.eq(Cat(ch.o))
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class AD9154NoSAWG(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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self.submodules.jesd = AD9154JESD(platform, sys_crg, jesd_crg, dac)
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self.sawgs = []
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for i, conv in enumerate(self.jesd.core.sink.flatten()):
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ramp = Signal(16)
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self.sync.rtio += ramp.eq(ramp + (1 << 9 + i))
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self.comb += conv.eq(Cat(ramp
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for i in range(len(conv) // len(ramp))))
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class Standalone(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x11000000,
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"rtio_dma": 0x12000000,
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"serwb": 0x13000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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platform = self.platform
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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"set_property CFGBVS VCCO [current_design]",
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"set_property CONFIG_VOLTAGE 3.3 [current_design]",
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])
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# forward RTM UART to second FTDI UART channel
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serial_1 = platform.request("serial", 1)
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serial_rtm = platform.request("serial_rtm")
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self.comb += [
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serial_1.tx.eq(serial_rtm.rx),
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serial_rtm.tx.eq(serial_1.rx)
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]
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# RTM bitstream upload
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rtm_fpga_cfg = platform.request("rtm_fpga_cfg")
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self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg)
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self.csr_devices.append("rtm_fpga_cfg")
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# AMC/RTM serwb
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serwb_pll = serwb.phy.SERWBPLL(125e6, 625e6, vco_div=2)
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self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk)
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self.submodules += serwb_pll
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serwb_pads = platform.request("amc_rtm_serwb")
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serwb_phy_amc = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="master")
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self.submodules.serwb_phy_amc = serwb_phy_amc
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self.csr_devices.append("serwb_phy_amc")
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serwb_phy_amc.serdes.cd_serwb_serdes.clk.attr.add("keep")
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serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk.attr.add("keep")
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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serwb_phy_amc.serdes.cd_serwb_serdes.clk,
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serwb_phy_amc.serdes.cd_serwb_serdes_5x.clk)
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serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave", with_scrambling=True)
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self.submodules += serwb_core
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
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# RTIO
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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if with_sawg:
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cls = AD9154
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else:
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cls = AD9154NoSAWG
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self.submodules.ad9154_crg = AD9154CRG(platform)
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self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
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self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
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self.csr_devices.append("ad9154_crg")
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self.csr_devices.append("ad9154_0")
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self.csr_devices.append("ad9154_1")
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self.config["HAS_AD9154"] = None
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self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
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self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
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rtio_channels.extend(rtio.Channel.from_phy(phy)
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for sawg in self.ad9154_0.sawgs +
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self.ad9154_1.sawgs
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for phy in sawg.phys)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.clock_domains.cd_rtio = ClockDomain()
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self.comb += [
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self.cd_rtio.clk.eq(ClockSignal("jesd")),
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self.cd_rtio.rst.eq(ResetSignal("jesd"))
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]
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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class Master(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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"rtio": 0x20000000,
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"rtio_dma": 0x30000000,
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"drtio_aux": 0x50000000,
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"mailbox": 0x70000000
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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**kwargs)
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AMPSoC.__init__(self)
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if with_sawg:
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warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.")
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules += Microscope(platform.request("serial", 1),
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self.clk_freq)
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# Si5324 used as a free-running oscillator, to avoid dependency on RTM.
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout"),
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data_pads=[platform.request("sfp", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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DRTIOMaster(self.drtio_transceiver.channels[0]))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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rtio_clk_period = 1e9/rtio_clk_freq
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for gth in self.drtio_transceiver.gths:
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platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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gth.txoutclk, gth.rxoutclk)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_core = rtio.Core(rtio_channels, glbl_fine_ts_width=3)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
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rtio.DMA(self.get_native_sdram_if()))
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self.register_kernel_cpu_csrdevice("rtio")
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri, self.drtio0.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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class Satellite(BaseSoC):
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mem_map = {
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"drtio_aux": 0x50000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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**kwargs)
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if with_sawg:
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warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.")
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platform = self.platform
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rtio_clk_freq = 150e6
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self.submodules += Microscope(platform.request("serial", 1),
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self.clk_freq)
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rtio_channels = []
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for i in range(4):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 0)
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self.comb += sma_io.direction.eq(1)
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phy = ttl_simple.Output(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sma_io = platform.request("sma_io", 1)
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self.comb += sma_io.direction.eq(0)
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phy = ttl_simple.InOut(sma_io.level)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("si5324_clkout"),
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data_pads=[platform.request("sfp", 0)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.drtio_transceiver.channels[0], rtio_channels,
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self.rx_synchronizer))
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|
self.csr_devices.append("drtio0")
|
|
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
|
|
self.drtio0.aux_controller.bus)
|
|
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
|
|
self.config["HAS_DRTIO"] = None
|
|
self.add_csr_group("drtio", ["drtio0"])
|
|
self.add_memory_group("drtio_aux", ["drtio0_aux"])
|
|
|
|
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
|
|
si5324_clkin = platform.request("si5324_clkin")
|
|
self.specials += \
|
|
Instance("OBUFDS",
|
|
i_I=ClockSignal("rtio_rx0"),
|
|
o_O=si5324_clkin.p, o_OB=si5324_clkin.n
|
|
)
|
|
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
|
|
self.csr_devices.append("si5324_rst_n")
|
|
i2c = self.platform.request("i2c")
|
|
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
|
self.csr_devices.append("i2c")
|
|
self.config["I2C_BUS_COUNT"] = 1
|
|
self.config["HAS_SI5324"] = None
|
|
|
|
rtio_clk_period = 1e9/rtio_clk_freq
|
|
gth = self.drtio_transceiver.gths[0]
|
|
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
|
|
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
|
|
platform.add_false_path_constraints(
|
|
self.crg.cd_sys.clk,
|
|
gth.txoutclk, gth.rxoutclk)
|
|
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="Sayma AMC gateware and firmware builder")
|
|
builder_args(parser)
|
|
soc_sdram_args(parser)
|
|
parser.set_defaults(output_dir="artiq_sayma")
|
|
parser.add_argument("-V", "--variant", default="standalone",
|
|
help="variant: "
|
|
"standalone/master/satellite "
|
|
"(default: %(default)s)")
|
|
parser.add_argument("--rtm-csr-csv",
|
|
default=os.path.join("artiq_sayma", "rtm_gateware", "rtm_csr.csv"),
|
|
help="CSV file listing remote CSRs on RTM (default: %(default)s)")
|
|
parser.add_argument("--without-sawg",
|
|
default=False, action="store_true",
|
|
help="Remove SAWG RTIO channels feeding the JESD links (speeds up "
|
|
"compilation time). Replaces them with fixed sawtooth generators.")
|
|
args = parser.parse_args()
|
|
|
|
variant = args.variant.lower()
|
|
if variant == "standalone":
|
|
cls = Standalone
|
|
elif variant == "master":
|
|
cls = Master
|
|
elif variant == "satellite":
|
|
cls = Satellite
|
|
else:
|
|
raise SystemExit("Invalid variant (-V/--variant)")
|
|
soc = cls(with_sawg=not args.without_sawg, **soc_sdram_argdict(args))
|
|
|
|
# DRTIO variants do not use the RTM yet.
|
|
if variant not in {"master", "satellite"}:
|
|
remote_csr_regions = remote_csr.get_remote_csr_regions(
|
|
soc.mem_map["serwb"] | soc.shadow_base,
|
|
args.rtm_csr_csv)
|
|
for name, origin, busword, csrs in remote_csr_regions:
|
|
soc.add_csr_region(name, origin, busword, csrs)
|
|
# Configuration for RTM peripherals. Keep in sync with sayma_rtm.py!
|
|
soc.config["HAS_HMC830_7043"] = None
|
|
soc.config["CONVERTER_SPI_HMC830_CS"] = 0
|
|
soc.config["CONVERTER_SPI_HMC7043_CS"] = 1
|
|
soc.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 2
|
|
|
|
build_artiq_soc(soc, builder_argdict(args))
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|