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sayma: enable 2X DAC interpolation 

Seems to work just fine and gets one clock divider out of the way.
This commit is contained in:
Sebastien Bourdeauducq 2019-01-24 18:28:01 +08:00
parent 07b5b0d36d
commit f8b39b0b9a
2 changed files with 2 additions and 2 deletions
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2
artiq/firmware/libboard_artiq/ad9154.rs
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@ -184,7 +184,7 @@ fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
write(ad9154_reg::SPI_PAGEINDX, 0x3); // A and B dual write(ad9154_reg::SPI_PAGEINDX, 0x3); // A and B dual
write(ad9154_reg::INTERP_MODE, 0); // 1x write(ad9154_reg::INTERP_MODE, 0x01); // 2x
write(ad9154_reg::MIX_MODE, 0); write(ad9154_reg::MIX_MODE, 0);
write(ad9154_reg::DATA_FORMAT, 0*ad9154_reg::BINARY_FORMAT); // s16 write(ad9154_reg::DATA_FORMAT, 0*ad9154_reg::BINARY_FORMAT); // s16
write(ad9154_reg::DATAPATH_CTRL, write(ad9154_reg::DATAPATH_CTRL,

2
artiq/firmware/libboard_artiq/hmc830_7043.rs
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@ -156,7 +156,7 @@ pub mod hmc7043 {
use board_misoc::{csr, clock}; use board_misoc::{csr, clock};
// All frequencies assume 1.2GHz HMC830 output // All frequencies assume 1.2GHz HMC830 output
const DAC_CLK_DIV: u16 = 2; // 600MHz const DAC_CLK_DIV: u16 = 1; // 1200MHz
const FPGA_CLK_DIV: u16 = 8; // 150MHz const FPGA_CLK_DIV: u16 = 8; // 150MHz
const SYSREF_DIV: u16 = 128; // 9.375MHz const SYSREF_DIV: u16 = 128; // 9.375MHz
const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz) const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)