From f8b39b0b9a986b7e43ef386ca92bfebc28f7d6ee Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 24 Jan 2019 18:28:01 +0800 Subject: [PATCH] sayma: enable 2X DAC interpolation Seems to work just fine and gets one clock divider out of the way. --- artiq/firmware/libboard_artiq/ad9154.rs | 2 +- artiq/firmware/libboard_artiq/hmc830_7043.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index e9b7db5db..5b876b371 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -184,7 +184,7 @@ fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> { write(ad9154_reg::SPI_PAGEINDX, 0x3); // A and B dual - write(ad9154_reg::INTERP_MODE, 0); // 1x + write(ad9154_reg::INTERP_MODE, 0x01); // 2x write(ad9154_reg::MIX_MODE, 0); write(ad9154_reg::DATA_FORMAT, 0*ad9154_reg::BINARY_FORMAT); // s16 write(ad9154_reg::DATAPATH_CTRL, diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index 2b381e60d..8156c5d36 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -156,7 +156,7 @@ pub mod hmc7043 { use board_misoc::{csr, clock}; // All frequencies assume 1.2GHz HMC830 output - const DAC_CLK_DIV: u16 = 2; // 600MHz + const DAC_CLK_DIV: u16 = 1; // 1200MHz const FPGA_CLK_DIV: u16 = 8; // 150MHz const SYSREF_DIV: u16 = 128; // 9.375MHz const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)