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dsp/test: skip and fix sat_add

This commit is contained in:
Robert Jördens 2017-06-22 18:01:26 +02:00
parent 47928a2c0d
commit f78d5a87e9
1 changed files with 9 additions and 5 deletions
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14
artiq/gateware/test/dsp/test_satadd.py
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@ -12,13 +12,15 @@ class DUT(mg.Module, SatAddMixin):
self.l0 = mg.Signal.like(self.o) self.l0 = mg.Signal.like(self.o)
self.l1 = mg.Signal.like(self.o) self.l1 = mg.Signal.like(self.o)
self.c = mg.Signal(2) self.c = mg.Signal(2)
self.comb += self.o.eq(self.sat_add(self.i0, self.i1, self.comb += self.o.eq(self.sat_add((self.i0, self.i1),
limits=(self.l0, self.l1), clipped=self.c)) width=4, limits=(self.l0, self.l1), clipped=self.c))
class SatAddTest(unittest.TestCase): class SatAddTest(unittest.TestCase):
def setUp(self): def setUp(self):
self.dut = DUT(width=4) self.dut = DUT(width=4)
# import migen.fhdl.verilog
# print(mg.fhdl.verilog.convert(self.dut))
def _sweep(self): def _sweep(self):
def gen(): def gen():
@ -39,13 +41,13 @@ class SatAddTest(unittest.TestCase):
full = i0 + i1 full = i0 + i1
lim = full lim = full
clip = 0
if full < l0: if full < l0:
lim = l0 lim = l0
clip = 1
if full > l1: if full > l1:
lim = l1 lim = l1
if l1 < full < l0: clip = 2
lim = 0
clip = int(full < l0) | (int(full > l1) << 1)
with self.subTest(i0=i0, i1=i1): with self.subTest(i0=i0, i1=i1):
self.assertEqual(lim, o) self.assertEqual(lim, o)
self.assertEqual(clip, c) self.assertEqual(clip, c)
@ -56,9 +58,11 @@ class SatAddTest(unittest.TestCase):
def test_inst(self): def test_inst(self):
pass pass
@unittest.skip("limiter disabled")
def test_run(self): def test_run(self):
self._sweep() self._sweep()
@unittest.skip("limiter disabled")
def test_limits(self): def test_limits(self):
for l0 in -8, 0, 1, 7: for l0 in -8, 0, 1, 7:
for l1 in -8, 0, 1, 7: for l1 in -8, 0, 1, 7: