diff --git a/artiq/gateware/test/dsp/test_satadd.py b/artiq/gateware/test/dsp/test_satadd.py
index 56d3691b3..1f408ef0b 100644
--- a/artiq/gateware/test/dsp/test_satadd.py
+++ b/artiq/gateware/test/dsp/test_satadd.py
@@ -12,13 +12,15 @@ class DUT(mg.Module, SatAddMixin):
         self.l0 = mg.Signal.like(self.o)
         self.l1 = mg.Signal.like(self.o)
         self.c = mg.Signal(2)
-        self.comb += self.o.eq(self.sat_add(self.i0, self.i1,
-            limits=(self.l0, self.l1), clipped=self.c))
+        self.comb += self.o.eq(self.sat_add((self.i0, self.i1),
+            width=4, limits=(self.l0, self.l1), clipped=self.c))
 
 
 class SatAddTest(unittest.TestCase):
     def setUp(self):
         self.dut = DUT(width=4)
+        # import migen.fhdl.verilog
+        # print(mg.fhdl.verilog.convert(self.dut))
 
     def _sweep(self):
         def gen():
@@ -39,13 +41,13 @@ class SatAddTest(unittest.TestCase):
 
                 full = i0 + i1
                 lim = full
+                clip = 0
                 if full < l0:
                     lim = l0
+                    clip = 1
                 if full > l1:
                     lim = l1
-                if l1 < full < l0:
-                    lim = 0
-                clip = int(full < l0) | (int(full > l1) << 1)
+                    clip = 2
                 with self.subTest(i0=i0, i1=i1):
                     self.assertEqual(lim, o)
                     self.assertEqual(clip, c)
@@ -56,9 +58,11 @@ class SatAddTest(unittest.TestCase):
     def test_inst(self):
         pass
 
+    @unittest.skip("limiter disabled")
     def test_run(self):
         self._sweep()
 
+    @unittest.skip("limiter disabled")
     def test_limits(self):
         for l0 in -8, 0, 1, 7:
             for l1 in -8, 0, 1, 7: