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runtime mgmt: remove cursor

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occheung 2024-09-05 11:59:10 +08:00
parent a56294f9de
commit f2f27e2d30
1 changed files with 2 additions and 2 deletions
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artiq/firmware/runtime/mgmt.rs
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@ -398,11 +398,11 @@ mod remote_coremgmt {
routing_table: &drtio_routing::RoutingTable, linkno: u8, routing_table: &drtio_routing::RoutingTable, linkno: u8,
destination: u8, stream: &mut TcpStream, key: &String, value: &Vec<u8>, destination: u8, stream: &mut TcpStream, key: &String, value: &Vec<u8>,
_restart_idle: &Urc<Cell<bool>>) -> Result<(), Error<SchedError>> { _restart_idle: &Urc<Cell<bool>>) -> Result<(), Error<SchedError>> {
let mut message = Cursor::new(Vec::with_capacity(key.len() + value.len() + 4 * 2)); let mut message = Vec::with_capacity(key.len() + value.len() + 4 * 2);
message.write_string(key).unwrap(); message.write_string(key).unwrap();
message.write_bytes(value).unwrap(); message.write_bytes(value).unwrap();
match drtio::partition_data(message.get_ref(), |slice, status, len: usize| { match drtio::partition_data(&message, |slice, status, len: usize| {
let reply = drtio::aux_transact(io, aux_mutex, ddma_mutex, subkernel_mutex, routing_table, linkno, let reply = drtio::aux_transact(io, aux_mutex, ddma_mutex, subkernel_mutex, routing_table, linkno,
&Packet::CoreMgmtConfigWriteRequest { &Packet::CoreMgmtConfigWriteRequest {
destination: destination, length: len as u16, last: status.is_last(), data: *slice}); destination: destination, length: len as u16, last: status.is_last(), data: *slice});