mirror of https://github.com/m-labs/artiq.git
348 lines
14 KiB
Python
348 lines
14 KiB
Python
from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.cores.code_8b10b import Encoder, Decoder
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from misoc.interconnect.csr import *
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from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
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from artiq.gateware.drtio.transceiver.clock_aligner import BruteforceClockAligner
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from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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class GTX_20X(Module, TransceiverInterface):
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# Settings:
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# * GTX reference clock (at clock_pads) @ 125MHz == coarse RTIO frequency
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# * GTX data width = 20
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# * GTX PLL frequency @ 2.5GHz
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# * GTX line rate (TX & RX) @ 2.5Gb/s
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# * GTX TX/RX USRCLK @ 125MHz == coarse RTIO frequency
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def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq):
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encoder = ClockDomainsRenamer("rtio")(
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Encoder(2, True))
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self.submodules += encoder
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decoders = [ClockDomainsRenamer("rtio_rx0")(
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(Decoder(True))) for _ in range(2)]
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self.submodules += decoders
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TransceiverInterface.__init__(self, [ChannelInterface(encoder, decoders)])
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# transceiver direct clock outputs
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# useful to specify clock constraints in a way palatable to Vivado
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self.txoutclk = Signal()
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self.rxoutclk = Signal()
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# # #
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refclk = Signal()
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stable_clkin_n = Signal()
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self.stable_clkin.storage.attr.add("no_retiming")
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self.comb += stable_clkin_n.eq(~self.stable_clkin.storage)
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=stable_clkin_n,
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_O=refclk
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)
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cpllreset = Signal()
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cplllock = Signal()
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# TX generates RTIO clock, init must be in system domain
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tx_init = GTXInit(sys_clk_freq, False)
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# RX receives restart commands from RTIO domain
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rx_init = ClockDomainsRenamer("rtio")(
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GTXInit(self.rtio_clk_freq, True))
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self.submodules += tx_init, rx_init
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self.comb += [
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cpllreset.eq(tx_init.cpllreset),
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tx_init.cplllock.eq(cplllock),
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rx_init.cplllock.eq(cplllock)
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]
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txdata = Signal(20)
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rxdata = Signal(20)
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self.specials += \
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Instance("GTXE2_CHANNEL",
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# PMA Attributes
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p_PMA_RSV=0x00018480,
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p_PMA_RSV2=0x2050, # PMA_RSV2[5] = 0: Eye scan feature disabled
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p_PMA_RSV3=0,
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p_PMA_RSV4=1, # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
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p_RX_BIAS_CFG=0b000000000100,
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p_RX_OS_CFG=0b0000010000000,
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p_RX_CLK25_DIV=5,
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p_TX_CLK25_DIV=5,
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# Power-Down Attributes
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p_PD_TRANS_TIME_FROM_P2=0x3c,
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p_PD_TRANS_TIME_NONE_P2=0x3c,
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p_PD_TRANS_TIME_TO_P2=0x64,
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# CPLL
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p_CPLL_CFG=0xBC07DC,
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p_CPLL_FBDIV=4,
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p_CPLL_FBDIV_45=5,
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p_CPLL_REFCLK_DIV=1,
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p_RXOUT_DIV=2,
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p_TXOUT_DIV=2,
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i_CPLLRESET=cpllreset,
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i_CPLLPD=cpllreset,
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o_CPLLLOCK=cplllock,
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i_CPLLLOCKEN=1,
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i_CPLLREFCLKSEL=0b001,
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i_TSTIN=2**20-1,
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i_GTREFCLK0=refclk,
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# TX clock
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p_TXBUF_EN="FALSE",
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p_TX_XCLK_SEL="TXUSR",
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o_TXOUTCLK=self.txoutclk,
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i_TXSYSCLKSEL=0b00,
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i_TXOUTCLKSEL=0b11,
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# TX Startup/Reset
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i_GTTXRESET=tx_init.gtXxreset,
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o_TXRESETDONE=tx_init.Xxresetdone,
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i_TXDLYSRESET=tx_init.Xxdlysreset,
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o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone,
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o_TXPHALIGNDONE=tx_init.Xxphaligndone,
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i_TXUSERRDY=tx_init.Xxuserrdy,
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p_TXPMARESET_TIME=1,
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p_TXPCSRESET_TIME=1,
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i_TXINHIBIT=~self.txenable.storage,
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# TX data
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p_TX_DATA_WIDTH=20,
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p_TX_INT_DATAWIDTH=0,
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i_TXCHARDISPMODE=Cat(txdata[9], txdata[19]),
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i_TXCHARDISPVAL=Cat(txdata[8], txdata[18]),
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i_TXDATA=Cat(txdata[:8], txdata[10:18]),
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i_TXUSRCLK=ClockSignal("rtio"),
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i_TXUSRCLK2=ClockSignal("rtio"),
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# TX electrical
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i_TXBUFDIFFCTRL=0b100,
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i_TXDIFFCTRL=0b1000,
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# RX Startup/Reset
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i_GTRXRESET=rx_init.gtXxreset,
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o_RXRESETDONE=rx_init.Xxresetdone,
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i_RXDLYSRESET=rx_init.Xxdlysreset,
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o_RXDLYSRESETDONE=rx_init.Xxdlysresetdone,
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o_RXPHALIGNDONE=rx_init.Xxphaligndone,
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i_RXUSERRDY=rx_init.Xxuserrdy,
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p_RXPMARESET_TIME=1,
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p_RXPCSRESET_TIME=1,
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# RX AFE
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p_RX_DFE_XYD_CFG=0,
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p_RX_CM_SEL=0b11, # RX_CM_SEL = 0b11: Common mode is programmable
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p_RX_CM_TRIM=0b010, # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
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i_RXDFEXYDEN=1,
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i_RXDFEXYDHOLD=0,
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i_RXDFEXYDOVRDEN=0,
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i_RXLPMEN=0, # RXLPMEN = 0: DFE mode is enabled
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p_RX_DFE_GAIN_CFG=0x0207EA,
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p_RX_DFE_VP_CFG=0b00011111100000011,
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p_RX_DFE_UT_CFG=0b10001000000000000,
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p_RX_DFE_KL_CFG=0b0000011111110,
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p_RX_DFE_KL_CFG2=0x3788140A,
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p_RX_DFE_H2_CFG=0b000110000000,
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p_RX_DFE_H3_CFG=0b000110000000,
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p_RX_DFE_H4_CFG=0b00011100000,
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p_RX_DFE_H5_CFG=0b00011100000,
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p_RX_DFE_LPM_CFG=0x0904, # RX_DFE_LPM_CFG = 0x0904: linerate <= 6.6Gb/s
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# = 0x0104: linerate > 6.6Gb/s
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# RX clock
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i_RXDDIEN=1,
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i_RXSYSCLKSEL=0b00,
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i_RXOUTCLKSEL=0b010,
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o_RXOUTCLK=self.rxoutclk,
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i_RXUSRCLK=ClockSignal("rtio_rx0"),
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i_RXUSRCLK2=ClockSignal("rtio_rx0"),
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# RX Clock Correction Attributes
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p_CLK_CORRECT_USE="FALSE",
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p_CLK_COR_SEQ_1_1=0b0100000000,
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p_CLK_COR_SEQ_2_1=0b0100000000,
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p_CLK_COR_SEQ_1_ENABLE=0b1111,
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p_CLK_COR_SEQ_2_ENABLE=0b1111,
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# RX data
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p_RX_DATA_WIDTH=20,
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p_RX_INT_DATAWIDTH=0,
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o_RXDISPERR=Cat(rxdata[9], rxdata[19]),
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o_RXCHARISK=Cat(rxdata[8], rxdata[18]),
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o_RXDATA=Cat(rxdata[:8], rxdata[10:18]),
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# RX Byte and Word Alignment Attributes
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p_ALIGN_COMMA_DOUBLE="FALSE",
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p_ALIGN_COMMA_ENABLE=0b1111111111,
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p_ALIGN_COMMA_WORD=1,
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p_ALIGN_MCOMMA_DET="TRUE",
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p_ALIGN_MCOMMA_VALUE=0b1010000011,
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p_ALIGN_PCOMMA_DET="TRUE",
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p_ALIGN_PCOMMA_VALUE=0b0101111100,
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p_SHOW_REALIGN_COMMA="FALSE",
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p_RXSLIDE_AUTO_WAIT=7,
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p_RXSLIDE_MODE="PCS",
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p_RX_SIG_VALID_DLY=10,
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# RX 8B/10B Decoder Attributes
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p_RX_DISPERR_SEQ_MATCH="FALSE",
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p_DEC_MCOMMA_DETECT="TRUE",
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p_DEC_PCOMMA_DETECT="TRUE",
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p_DEC_VALID_COMMA_ONLY="FALSE",
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# RX Buffer Attributes
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p_RXBUF_ADDR_MODE="FAST",
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p_RXBUF_EIDLE_HI_CNT=0b1000,
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p_RXBUF_EIDLE_LO_CNT=0b0000,
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p_RXBUF_EN="FALSE",
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p_RX_BUFFER_CFG=0b000000,
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p_RXBUF_RESET_ON_CB_CHANGE="TRUE",
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p_RXBUF_RESET_ON_COMMAALIGN="FALSE",
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p_RXBUF_RESET_ON_EIDLE="FALSE", # RXBUF_RESET_ON_EIDLE = FALSE: OOB is disabled
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p_RXBUF_RESET_ON_RATE_CHANGE="TRUE",
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p_RXBUFRESET_TIME=0b00001,
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p_RXBUF_THRESH_OVFLW=61,
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p_RXBUF_THRESH_OVRD="FALSE",
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p_RXBUF_THRESH_UNDFLW=4,
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p_RXDLY_CFG=0x001F,
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p_RXDLY_LCFG=0x030,
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p_RXDLY_TAP_CFG=0x0000,
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p_RXPH_CFG=0xC00002,
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p_RXPHDLY_CFG=0x084020,
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p_RXPH_MONITOR_SEL=0b00000,
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p_RX_XCLK_SEL="RXUSR",
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p_RX_DDI_SEL=0b000000,
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p_RX_DEFER_RESET_BUF_EN="TRUE",
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# CDR Attributes
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p_RXCDR_CFG=0x03000023FF20400020, # DFE @ <= 6.6Gb/s, scrambled, CDR setting < +/- 200ppm
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# (See UG476 (v1.12.1), p.206)
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p_RXCDR_FR_RESET_ON_EIDLE=0b0,
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p_RXCDR_HOLD_DURING_EIDLE=0b0,
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p_RXCDR_PH_RESET_ON_EIDLE=0b0,
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p_RXCDR_LOCK_CFG=0b010101,
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# # RX Initialization and Reset Attributes
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# p_RXCDRFREQRESET_TIME=0b00001,
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# p_RXCDRPHRESET_TIME=0b00001,
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# p_RXISCANRESET_TIME=0b00001,
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# p_RXPCSRESET_TIME=0b00001,
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# p_RXPMARESET_TIME=0b00011,
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# Pads
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i_GTXRXP=rx_pads.p,
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i_GTXRXN=rx_pads.n,
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o_GTXTXP=tx_pads.p,
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o_GTXTXN=tx_pads.n,
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# Other parameters
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p_PCS_RSVD_ATTR=0x000, # PCS_RSVD_ATTR[1] = 0: TX Single Lane Auto Mode
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# [2] = 0: RX Single Lane Auto Mode
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# [8] = 0: OOB is disabled
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i_RXELECIDLEMODE=0b11, # RXELECIDLEMODE = 0b11: OOB is disabled
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p_RX_DFE_LPM_HOLD_DURING_EIDLE=0b0,
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p_ES_EYE_SCAN_EN="TRUE", # Must be TRUE for GTX
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)
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tx_reset_deglitched = Signal()
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tx_reset_deglitched.attr.add("no_retiming")
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self.sync += tx_reset_deglitched.eq(~tx_init.done)
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self.specials += [
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Instance("BUFG", i_I=self.txoutclk, o_O=self.cd_rtio.clk),
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AsyncResetSynchronizer(self.cd_rtio, tx_reset_deglitched)
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]
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rx_reset_deglitched = Signal()
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rx_reset_deglitched.attr.add("no_retiming")
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self.sync.rtio += rx_reset_deglitched.eq(~rx_init.done)
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self.specials += [
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Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_rtio_rx0.clk),
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AsyncResetSynchronizer(self.cd_rtio_rx0, rx_reset_deglitched)
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]
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chan = self.channels[0]
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self.comb += [
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txdata.eq(Cat(chan.encoder.output[0], chan.encoder.output[1])),
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chan.decoders[0].input.eq(rxdata[:10]),
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chan.decoders[1].input.eq(rxdata[10:])
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]
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clock_aligner = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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BruteforceClockAligner(0b0101111100, self.rtio_clk_freq))
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self.submodules += clock_aligner
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self.comb += [
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clock_aligner.rxdata.eq(rxdata),
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rx_init.restart.eq(clock_aligner.restart),
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chan.rx_ready.eq(clock_aligner.ready)
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]
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class GTX_1000BASE_BX10(GTX_20X):
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rtio_clk_freq = 125e6
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class RXSynchronizer(Module, AutoCSR):
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"""Delays the data received in the rtio_rx domain by a configurable amount
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so that it meets s/h in the rtio domain, and recapture it in the rtio
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domain. This has fixed latency.
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Since Xilinx doesn't provide decent on-chip delay lines, we implement the
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delay with MMCM that provides a clock and a finely configurable phase, used
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to resample the data.
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The phase has to be determined either empirically or by making sense of the
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Xilinx scriptures (when existent) and should be constant for a given design
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placement.
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"""
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def __init__(self, rtio_clk_freq, initial_phase=0.0):
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self.phase_shift = CSR()
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self.phase_shift_done = CSRStatus()
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self.clock_domains.cd_rtio_delayed = ClockDomain()
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mmcm_output = Signal()
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mmcm_fb = Signal()
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mmcm_locked = Signal()
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# maximize VCO frequency to maximize phase shift resolution
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mmcm_mult = 1200e6//rtio_clk_freq
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self.specials += [
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Instance("MMCME2_ADV",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio_rx"),
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i_RST=ResetSignal("rtio_rx"),
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i_CLKINSEL=1, # yes, 1=CLKIN1 0=CLKIN2
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p_CLKFBOUT_MULT_F=mmcm_mult,
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p_CLKOUT0_DIVIDE_F=mmcm_mult,
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p_CLKOUT0_PHASE=initial_phase,
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p_DIVCLK_DIVIDE=1,
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# According to Xilinx, there is no guarantee of input/output
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# phase relationship when using internal feedback. We assume
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# here that the input/ouput skew is constant to save BUFGs.
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o_CLKFBOUT=mmcm_fb,
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i_CLKFBIN=mmcm_fb,
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p_CLKOUT0_USE_FINE_PS="TRUE",
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o_CLKOUT0=mmcm_output,
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o_LOCKED=mmcm_locked,
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i_PSCLK=ClockSignal(),
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i_PSEN=self.phase_shift.re,
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i_PSINCDEC=self.phase_shift.r,
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o_PSDONE=self.phase_shift_done.status,
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),
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Instance("BUFR", i_I=mmcm_output, o_O=self.cd_rtio_delayed.clk),
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AsyncResetSynchronizer(self.cd_rtio_delayed, ~mmcm_locked)
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]
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def resync(self, signal):
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delayed = Signal.like(signal, related=signal)
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synchronized = Signal.like(signal, related=signal)
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self.sync.rtio_delayed += delayed.eq(signal)
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self.sync.rtio += synchronized.eq(delayed)
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return synchronized
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