mirror of https://github.com/m-labs/artiq.git
227 lines
7.5 KiB
Python
227 lines
7.5 KiB
Python
from math import ceil
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from functools import reduce
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from operator import add
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from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.genlib.misc import WaitTimer
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from migen.genlib.fsm import FSM
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class GTXInit(Module):
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# Based on LiteSATA by Enjoy-Digital
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def __init__(self, sys_clk_freq, rx):
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self.done = Signal()
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self.restart = Signal()
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# GTX signals
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self.cplllock = Signal()
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self.gtXxreset = Signal()
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self.Xxresetdone = Signal()
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self.Xxdlysreset = Signal()
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self.Xxdlysresetdone = Signal()
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self.Xxphaligndone = Signal()
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self.Xxuserrdy = Signal()
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# # #
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# Double-latch transceiver asynch outputs
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cplllock = Signal()
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Xxresetdone = Signal()
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Xxdlysresetdone = Signal()
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Xxphaligndone = Signal()
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self.specials += [
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MultiReg(self.cplllock, cplllock),
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MultiReg(self.Xxresetdone, Xxresetdone),
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MultiReg(self.Xxdlysresetdone, Xxdlysresetdone),
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MultiReg(self.Xxphaligndone, Xxphaligndone),
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]
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# Deglitch FSM outputs driving transceiver asynch inputs
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gtXxreset = Signal()
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Xxdlysreset = Signal()
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Xxuserrdy = Signal()
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self.sync += [
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self.gtXxreset.eq(gtXxreset),
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self.Xxdlysreset.eq(Xxdlysreset),
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self.Xxuserrdy.eq(Xxuserrdy)
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]
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# After configuration, transceiver resets have to stay low for
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# at least 500ns (see AR43482)
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startup_cycles = ceil(500*sys_clk_freq/1000000000)
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startup_timer = WaitTimer(startup_cycles)
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self.submodules += startup_timer
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startup_fsm = FSM(reset_state="INITIAL")
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self.submodules += startup_fsm
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if rx:
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cdr_stable_timer = WaitTimer(1024)
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self.submodules += cdr_stable_timer
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Xxphaligndone_r = Signal(reset=1)
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Xxphaligndone_rising = Signal()
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self.sync += Xxphaligndone_r.eq(Xxphaligndone)
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self.comb += Xxphaligndone_rising.eq(Xxphaligndone & ~Xxphaligndone_r)
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startup_fsm.act("INITIAL",
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startup_timer.wait.eq(1),
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If(startup_timer.done, NextState("RESET_GTX"))
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)
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startup_fsm.act("RESET_GTX",
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gtXxreset.eq(1),
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NextState("WAIT_CPLL")
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)
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startup_fsm.act("WAIT_CPLL",
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gtXxreset.eq(1),
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If(cplllock, NextState("RELEASE_RESET"))
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)
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# Release GTX reset and wait for GTX resetdone
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# (from UG476, GTX is reset on falling edge
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# of gttxreset)
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if rx:
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startup_fsm.act("RELEASE_RESET",
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Xxuserrdy.eq(1),
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cdr_stable_timer.wait.eq(1),
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If(Xxresetdone & cdr_stable_timer.done, NextState("ALIGN"))
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)
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else:
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startup_fsm.act("RELEASE_RESET",
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Xxuserrdy.eq(1),
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If(Xxresetdone, NextState("ALIGN"))
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)
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# Start delay alignment (pulse)
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startup_fsm.act("ALIGN",
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Xxuserrdy.eq(1),
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Xxdlysreset.eq(1),
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NextState("WAIT_ALIGN")
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)
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# Wait for delay alignment
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startup_fsm.act("WAIT_ALIGN",
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Xxuserrdy.eq(1),
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If(Xxdlysresetdone, NextState("WAIT_FIRST_ALIGN_DONE"))
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)
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# Wait 2 rising edges of rxphaligndone
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# (from UG476 in buffer bypass config)
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startup_fsm.act("WAIT_FIRST_ALIGN_DONE",
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Xxuserrdy.eq(1),
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If(Xxphaligndone_rising, NextState("WAIT_SECOND_ALIGN_DONE"))
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)
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startup_fsm.act("WAIT_SECOND_ALIGN_DONE",
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Xxuserrdy.eq(1),
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If(Xxphaligndone_rising, NextState("READY"))
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)
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startup_fsm.act("READY",
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Xxuserrdy.eq(1),
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self.done.eq(1),
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If(self.restart, NextState("RESET_GTX"))
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)
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# Changes the phase of the transceiver RX clock to align the comma to
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# the LSBs of RXDATA, fixing the latency.
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#
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# This is implemented by repeatedly resetting the transceiver until it
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# gives out the correct phase. Each reset gives a random phase.
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#
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# If Xilinx had designed the GTX transceiver correctly, RXSLIDE_MODE=PMA
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# would achieve this faster and in a cleaner way. But:
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# * the phase jumps are of 2 UI at every second RXSLIDE pulse, instead
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# of 1 UI at every pulse. It is unclear what the latency becomes.
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# * RXSLIDE_MODE=PMA cannot be used with the RX buffer bypassed.
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# Those design flaws make RXSLIDE_MODE=PMA yet another broken and useless
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# transceiver "feature".
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#
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# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
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# compared to the usual 8b10b binary representation.
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class BruteforceClockAligner(Module):
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def __init__(self, comma, rtio_clk_freq, check_period=6e-3):
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self.rxdata = Signal(20)
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self.restart = Signal()
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self.ready = Signal()
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check_max_val = ceil(check_period*rtio_clk_freq)
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check_counter = Signal(max=check_max_val+1)
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check = Signal()
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reset_check_counter = Signal()
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self.sync.rtio += [
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check.eq(0),
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If(reset_check_counter,
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check_counter.eq(check_max_val)
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).Else(
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If(check_counter == 0,
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check.eq(1),
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check_counter.eq(check_max_val)
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).Else(
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check_counter.eq(check_counter-1)
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)
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)
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]
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checks_reset = PulseSynchronizer("rtio", "rtio_rx")
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self.submodules += checks_reset
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comma_n = ~comma & 0b1111111111
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comma_seen_rxclk = Signal()
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comma_seen = Signal()
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comma_seen_rxclk.attr.add("no_retiming")
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self.specials += MultiReg(comma_seen_rxclk, comma_seen)
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self.sync.rtio_rx += \
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If(checks_reset.o,
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comma_seen_rxclk.eq(0)
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).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n),
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comma_seen_rxclk.eq(1)
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)
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error_seen_rxclk = Signal()
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error_seen = Signal()
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error_seen_rxclk.attr.add("no_retiming")
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self.specials += MultiReg(error_seen_rxclk, error_seen)
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rx1cnt = Signal(max=11)
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self.sync.rtio_rx += [
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rx1cnt.eq(reduce(add, [self.rxdata[i] for i in range(10)])),
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If(checks_reset.o,
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error_seen_rxclk.eq(0)
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).Elif((rx1cnt != 4) & (rx1cnt != 5) & (rx1cnt != 6),
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error_seen_rxclk.eq(1)
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)
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]
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fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="WAIT_COMMA"))
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self.submodules += fsm
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fsm.act("WAIT_COMMA",
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If(check,
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# Errors are still OK at this stage, as the transceiver
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# has just been reset and may output garbage data.
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If(comma_seen,
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NextState("WAIT_NOERROR")
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).Else(
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self.restart.eq(1)
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),
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checks_reset.i.eq(1)
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)
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)
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fsm.act("WAIT_NOERROR",
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If(check,
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If(comma_seen & ~error_seen,
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NextState("READY")
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).Else(
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self.restart.eq(1),
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NextState("WAIT_COMMA")
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),
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checks_reset.i.eq(1)
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)
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)
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fsm.act("READY",
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reset_check_counter.eq(1),
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self.ready.eq(1),
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If(error_seen,
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checks_reset.i.eq(1),
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self.restart.eq(1),
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NextState("WAIT_COMMA")
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)
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)
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