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hmc7043: disable GTP_CLK1 when not in use 

Termination and biasing are not active at the FPGA when IBUFDS_GTE3 is
not instantiated, and driving a clock then leads to overvoltage.
This commit is contained in:
Sebastien Bourdeauducq 2018-08-03 10:03:52 +08:00
parent 6fc8439399
commit e83ee3a07a
2 changed files with 6 additions and 0 deletions
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3
artiq/firmware/libboard_artiq/hmc830_7043.rs
View File

@ -171,7 +171,10 @@ pub mod hmc7043 {
(false, 0, 0x08), // 5: ADC2_SYSREF (false, 0, 0x08), // 5: ADC2_SYSREF
(true, FPGA_CLK_DIV, 0x08), // 6: GTP_CLK2 (true, FPGA_CLK_DIV, 0x08), // 6: GTP_CLK2
(true, SYSREF_DIV, 0x10), // 7: FPGA_DAC_SYSREF, LVDS (true, SYSREF_DIV, 0x10), // 7: FPGA_DAC_SYSREF, LVDS
#[cfg(hmc7043_enable_clk1)]
(true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1 (true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1
#[cfg(not(hmc7043_enable_clk1))]
(false, 0, 0x08), // 8: GTP_CLK1
(false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK (false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK
(false, 0, 0x10), // 10: RTM_MASTER_AUX_CLK (false, 0, 0x10), // 10: RTM_MASTER_AUX_CLK
(true, FPGA_CLK_DIV, 0x10), // 11: FPGA_ADC_SYSREF, LVDS -- repurposed for siphaser (true, FPGA_CLK_DIV, 0x10), // 11: FPGA_ADC_SYSREF, LVDS -- repurposed for siphaser

3
artiq/gateware/targets/sayma_amc.py
View File

@ -269,6 +269,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
sys_clk_freq=self.clk_freq, sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq) rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")
self.config["HMC7043_ENABLE_CLK1"] = None
drtio_csr_group = [] drtio_csr_group = []
drtio_memory_group = [] drtio_memory_group = []
@ -571,6 +572,8 @@ class Satellite(BaseSoC, RTMCommon):
sys_clk_freq=self.clk_freq, sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq) rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")
self.config["HMC7043_ENABLE_CLK1"] = None
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
self.submodules.drtio0 = rx0(DRTIOSatellite( self.submodules.drtio0 = rx0(DRTIOSatellite(