diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs
index 8a7b09dee..acb8af556 100644
--- a/artiq/firmware/libboard_artiq/hmc830_7043.rs
+++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs
@@ -171,7 +171,10 @@ pub mod hmc7043 {
         (false, 0,            0x08),  // 5: ADC2_SYSREF
         (true,  FPGA_CLK_DIV, 0x08),  // 6: GTP_CLK2
         (true,  SYSREF_DIV,   0x10),  // 7: FPGA_DAC_SYSREF, LVDS
+#[cfg(hmc7043_enable_clk1)]
         (true,  FPGA_CLK_DIV, 0x08),  // 8: GTP_CLK1
+#[cfg(not(hmc7043_enable_clk1))]
+        (false, 0,            0x08),  // 8: GTP_CLK1
         (false, 0,            0x10),  // 9: AMC_MASTER_AUX_CLK
         (false, 0,            0x10),  // 10: RTM_MASTER_AUX_CLK
         (true,  FPGA_CLK_DIV, 0x10),  // 11: FPGA_ADC_SYSREF, LVDS -- repurposed for siphaser
diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py
index b24bf88fa..8d7def6a0 100755
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@@ -269,6 +269,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon):
             sys_clk_freq=self.clk_freq,
             rtio_clk_freq=rtio_clk_freq)
         self.csr_devices.append("drtio_transceiver")
+        self.config["HMC7043_ENABLE_CLK1"] = None
 
         drtio_csr_group = []
         drtio_memory_group = []
@@ -571,6 +572,8 @@ class Satellite(BaseSoC, RTMCommon):
             sys_clk_freq=self.clk_freq,
             rtio_clk_freq=rtio_clk_freq)
         self.csr_devices.append("drtio_transceiver")
+        self.config["HMC7043_ENABLE_CLK1"] = None
+
         rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
         self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
         self.submodules.drtio0 = rx0(DRTIOSatellite(