From e80b4810322e8883bb946c0ee2accecfabb063be Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 5 Feb 2018 13:40:17 +0100 Subject: [PATCH] firmware/libboard_artiq/hmc830_7043.rs: add template for sys_ref phase configuration for dac1/dac2 and fpga --- artiq/firmware/libboard_artiq/hmc830_7043.rs | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index ee456beb9..7e5cf3971 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -180,10 +180,21 @@ mod hmc7043 { for &(addr, data) in HMC7043_WRITES.iter() { write(addr, data); } - /* sysref digital coarse delay configuration (18 steps, 1/2VCO cycle/step)*/ - write(0x112, 0x0); - /* sysref analog fine delay configuration (24 steps, 25ps/step)*/ - write(0x111, 0x0); + + /* dac1 sysref digital coarse delay configuration (17 steps, 1/2VCO cycle/step)*/ + write(0x0d6, 0); + /* dac1 sysref analog fine delay configuration (24 steps, 25ps/step)*/ + write(0x0d5, 0); + + /* dac2 sysref digital coarse delay configuration (17 steps, 1/2VCO cycle/step)*/ + write(0x0ea, 0); + /* dac2 sysref analog fine delay configuration (24 steps, 25ps/step)*/ + write(0x0e9, 0); + + /* fpga sysref digital coarse delay configuration (17 steps, 1/2VCO cycle/step)*/ + write(0x112, 0); + /* fpga sysref analog fine delay configuration (24 steps, 25ps/step)*/ + write(0x111, 0); Ok(()) }