From e6d17267546a8a8f97d2a2c1d2c4a2c15f992a67 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 22 Jun 2018 00:05:22 +0800 Subject: [PATCH] sayma: add RTIO log to DRTIO master --- artiq/gateware/targets/sayma_amc.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index ce469bacf..d0bd99450 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -313,6 +313,10 @@ class Master(MiniSoC, AMPSoC, RTMCommon): self.ad9154_1.sawgs for phy in sawg.phys) + self.config["HAS_RTIO_LOG"] = None + self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) + rtio_channels.append(rtio.LogChannel()) + self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj")