From e38187c760bda318a35c72269916d06ba3831fea Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 9 Mar 2018 00:49:07 +0800 Subject: [PATCH] drtio: increase default underflow margin. Closes #947 --- artiq/gateware/drtio/rt_controller_master.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/drtio/rt_controller_master.py b/artiq/gateware/drtio/rt_controller_master.py index ea325a1b8..24387bda2 100644 --- a/artiq/gateware/drtio/rt_controller_master.py +++ b/artiq/gateware/drtio/rt_controller_master.py @@ -19,7 +19,7 @@ class _CSRs(AutoCSR): self.tsc_correction = CSRStorage(64) self.set_time = CSR() - self.underflow_margin = CSRStorage(16, reset=200) + self.underflow_margin = CSRStorage(16, reset=300) self.o_get_buffer_space = CSR() self.o_dbg_buffer_space = CSRStatus(16)