M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

gateware.spi: ack only in cycles

This commit is contained in:
Robert Jördens 2016-02-29 17:29:37 +01:00
parent a0083f4501
commit dd570720ac
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/spi.py
View File

@ -310,7 +310,7 @@ class SPIMaster(Module):
spi.div_read.eq(config.div_read),
]
self.sync += [
bus.ack.eq(~bus.we | ~pending | spi.done),
bus.ack.eq(bus.cyc & bus.stb & (~bus.we | ~pending | spi.done)),
If(wb_we,
Array([data_write, xfer.raw_bits(), config.raw_bits()
])[bus.adr].eq(bus.dat_w)