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Update artiq/coredevice/phaser.py 

Co-authored-by: Robert Jördens <rj@quartiq.de>
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Norman Krackow 2022-06-17 14:40:07 +02:00 committed by GitHub
parent 2044dc3ae5
commit dc49372d57
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1 changed files with 3 additions and 1 deletions
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artiq/coredevice/phaser.py
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@ -1072,7 +1072,9 @@ class PhaserChannel:
data = 1
if hold == 1:
data = data | (1 << 1)
data = data | (profile << 2)
if bypass:
hold = 1
data = (profile << 2) | (hold << 1) | (bypass << 0)
self.phaser.write8(addr, data)
@kernel