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artiq
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Update artiq/coredevice/phaser.py 

Co-authored-by: Robert Jördens <rj@quartiq.de>
pull/1933/head
Norman Krackow 2022-06-17 14:39:37 +02:00 committed by GitHub
parent ae3f1c1c71
commit 2044dc3ae5
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1 changed files with 1 additions and 1 deletions
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artiq/coredevice/phaser.py
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@ -1067,7 +1067,7 @@ class PhaserChannel:
"""
if (profile < 0) | (profile > 3):
raise ValueError("invalid profile index")
addr = PHASER_ADDR_SERVO_CFG1 if self.index == 1 else PHASER_ADDR_SERVO_CFG0
addr = PHASER_ADDR_SERVO_CFG0 + self.index
if bypass == 0:
data = 1
if hold == 1: