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drtio: use BlindTransfer for error reporting

This commit is contained in:
Sebastien Bourdeauducq 2017-04-03 00:18:07 +08:00
parent 8c414cebc7
commit db3118b916
3 changed files with 14 additions and 12 deletions
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11
artiq/gateware/drtio/rt_errors_satellite.py
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@ -1,9 +1,10 @@
"""Protocol error reporting for satellites.""" """Protocol error reporting for satellites."""
from migen import * from migen import *
from migen.genlib.cdc import PulseSynchronizer
from misoc.interconnect.csr import * from misoc.interconnect.csr import *
from artiq.gateware.rtio.cdc import BlindTransfer
class RTErrorsSatellite(Module, AutoCSR): class RTErrorsSatellite(Module, AutoCSR):
def __init__(self, rt_packet, ios): def __init__(self, rt_packet, ios):
@ -13,12 +14,12 @@ class RTErrorsSatellite(Module, AutoCSR):
def error_csr(csr, *sources): def error_csr(csr, *sources):
for n, source in enumerate(sources): for n, source in enumerate(sources):
pending = Signal(related=source) pending = Signal(related=source)
ps = PulseSynchronizer("rtio", "sys") xfer = BlindTransfer(odomain="sys")
self.submodules += ps self.submodules += xfer
self.comb += ps.i.eq(source) self.comb += xfer.i.eq(source)
self.sync += [ self.sync += [
If(csr.re & csr.r[n], pending.eq(0)), If(csr.re & csr.r[n], pending.eq(0)),
If(ps.o, pending.eq(1)) If(xfer.o, pending.eq(1))
] ]
self.comb += csr.w[n].eq(pending) self.comb += csr.w[n].eq(pending)

6
artiq/gateware/drtio/rt_packet_master.py
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@ -5,7 +5,7 @@ from migen.genlib.fsm import *
from migen.genlib.fifo import AsyncFIFO from migen.genlib.fifo import AsyncFIFO
from migen.genlib.cdc import PulseSynchronizer from migen.genlib.cdc import PulseSynchronizer
from artiq.gateware.rtio.cdc import GrayCodeTransfer from artiq.gateware.rtio.cdc import GrayCodeTransfer, BlindTransfer
from artiq.gateware.drtio.rt_serializer import * from artiq.gateware.drtio.rt_serializer import *
@ -252,8 +252,8 @@ class RTPacketMaster(Module):
read_timestamp.eq(rx_dp.packet_as["read_reply"].timestamp) read_timestamp.eq(rx_dp.packet_as["read_reply"].timestamp)
] ]
err_unknown_packet_type = PulseSynchronizer("rtio_rx", "sys") err_unknown_packet_type = BlindTransfer("rtio_rx", "sys")
err_packet_truncated = PulseSynchronizer("rtio_rx", "sys") err_packet_truncated = BlindTransfer("rtio_rx", "sys")
self.submodules += err_unknown_packet_type, err_packet_truncated self.submodules += err_unknown_packet_type, err_packet_truncated
self.comb += [ self.comb += [
self.err_unknown_packet_type.eq(err_unknown_packet_type.o), self.err_unknown_packet_type.eq(err_unknown_packet_type.o),

9
artiq/gateware/rtio/cdc.py
View File

@ -47,15 +47,16 @@ class RTIOCounter(Module):
class BlindTransfer(Module): class BlindTransfer(Module):
def __init__(self): def __init__(self, idomain="rio", odomain="rsys"):
self.i = Signal() self.i = Signal()
self.o = Signal() self.o = Signal()
ps = PulseSynchronizer("rio", "rsys") ps = PulseSynchronizer(idomain, odomain)
ps_ack = PulseSynchronizer("rsys", "rio") ps_ack = PulseSynchronizer(odomain, idomain)
self.submodules += ps, ps_ack self.submodules += ps, ps_ack
blind = Signal() blind = Signal()
self.sync.rio += [ isync = getattr(self.sync, idomain)
isync += [
If(self.i, blind.eq(1)), If(self.i, blind.eq(1)),
If(ps_ack.o, blind.eq(0)) If(ps_ack.o, blind.eq(0))
] ]